Hi,
In the mptable.c for various CK804 boards, some settings are written into the LPC bridge's PCI configuration space. The comment just before this voodoo leads me to believe that these registers have something to do with interrupt mapping.
I've tried the values from the Asus A8N-E, they work better than the values I extracted from the stock bios on the MS-7135. (I think I'm making decent progress on this board.)
Anyway, I have an interrupt storm issue, and I have no idea how to debug it, short of trying all 79.2 octillion combinations that could be put in these three registers.
That or, of course, a holiday miracle of nvidia releasing chipset documentation.
But, somewhere between those two extremes may lie a feasible method. Or at least I can hope.
Any advice on what these registers should be programmed to?
(Thinking next time he'll insist on a documented chipset ...)
Jonathan Kollasch
On Mon, Dec 03, 2007 at 12:33:28AM -0600, jakllsch@kollasch.net wrote:
Hi,
In the mptable.c for various CK804 boards, some settings are written into the LPC bridge's PCI configuration space. The comment just before this voodoo leads me to believe that these registers have something to do with interrupt mapping.
I've tried the values from the Asus A8N-E, they work better than the values I extracted from the stock bios on the MS-7135. (I think I'm making decent progress on this board.)
Anyway, I have an interrupt storm issue, and I have no idea how to debug it, short of trying all 79.2 octillion combinations that could be put in these three registers.
That or, of course, a holiday miracle of nvidia releasing chipset documentation.
But, somewhere between those two extremes may lie a feasible method. Or at least I can hope.
Any advice on what these registers should be programmed to?
Well, apparently the stock values ... but you have to make sure other things also match stock values.
Sorry, for the rant.
Jonathan Kollasch
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jakllsch＠kollasch.net