CMOS post code offset

[Haleigh Novak]

Good Afternoon,

I was wondering if anyone could tell me what a valid input would be for coreboot's menuconfig->"console->Offset into CMOS to store POST codes"?  I have tried values in the (empty) null area (below with arrow <<---) [both 0x100000 and 0x200000], enabling the "General Setup->Use CMOS for configuration values", as well as enabling both of the following: "General Setup->Use CMOS for configuration values"  and "General Setup->Load default configuration values into CMOS on each boot (NEW)" - none of the above allow a successful compile. Would someone mind helping/directing me to when I can figure out what cmos offset to enter?

Thank you

H

from the bottom of a successful make:

Performing operation on 'COREBOOT' region...
Name                           Offset     Type         Size
cbfs master header             0x0        cbfs header  32
apu/amdfw                      0x80       raw          256
fallback/romstage              0x1c0      stage        380660
fallback/ramstage              0x5d140    stage        87603
config                         0x727c0    raw          200
revision                       0x728c0    raw          576
cmos_layout.bin                0x72b40    cmos_layout  1392
pci1002,9835.rom               0x73100    optionrom    59904
fallback/dsdt.aml              0x81b80    raw          5741
fallback/payload               0x83240    payload      61148
payload_config                 0x92180    raw          1563
payload_revision               0x92800    raw          237
(empty)                        0x92940    null         3592600        <<----
bootblock                      0x3ffb00   bootblock    912
    HOSTCC     cbfstool/rmodtool.o
    HOSTCC     cbfstool/rmodtool (link)
    HOSTCC     cbfstool/ifwitool.o
    HOSTCC     cbfstool/ifwitool (link)
Built asrock/imb-a180 (IMB-A180)

[Kyösti Mälkki]

Hi

You have confused non-volatile CMOS with SPI flash, the output of
cbfstool is about SPI flash and POST codes will not be stored there.

As AGESA platforms have some multiprocessor init in romstage, and
there is no spinlock available, CMOS reads and writes may not be
reliable. At the minimum you need to check BSP does not drive any
POSTs while it waits for APs, but as this happens in vendorcode those
POSTs would not be recorded anyway in CMOS.

If you still want the offset:

With USE_OPTION_TABLE=y, renaming in cmos.layout user_data to
cmos_post_offset might do it.
With USE_OPTION_TABLE=n same place, set CMOS_POST_OFFSET=91 (=728/8).

You probably get error message about invalid checksum in the log if
you use that offset, but that should not trigger loading of defaults.
You will also want someone to call cmos_post_log() at boot to show the
previously stored POST, I can't tell if DRIVERS_ELOG works with AGESA
out-of-the box.

Hope this helps,
Kyösti