Hi,
here's a patch for the Neoware Eon 4000s thin client, based on the info from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html
Thanks, Uwe.
On 10.07.2008 13:55, Uwe Hermann wrote:
Hi,
here's a patch for the Neoware Eon 4000s thin client, based on the info from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html
Looks nice. I wonder whether we really want this stuff to depend on ROMCC. Does CAR work for the GX1?
Regards, Carl-Daniel
On Fri, Jul 11, 2008 at 11:17:53PM +0200, Carl-Daniel Hailfinger wrote:
On 10.07.2008 13:55, Uwe Hermann wrote:
Hi,
here's a patch for the Neoware Eon 4000s thin client, based on the info from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html
Looks nice. I wonder whether we really want this stuff to depend on ROMCC.
On the long run: no. But that's for another patch (and requires lots more work).
Does CAR work for the GX1?
Not yet, but it's possible to do. I think Juergen Beisert (CC'd) wrote something for GX1 in v3 a while ago (?) Juergen, do you still have that code and will it work for v3 (and even better, also for v2)? If so, please post it with a Signed-off-by so we can get it into svn.
Uwe.
Hi Uwe,
On Sonntag, 13. Juli 2008, Uwe Hermann wrote:
On Fri, Jul 11, 2008 at 11:17:53PM +0200, Carl-Daniel Hailfinger wrote:
On 10.07.2008 13:55, Uwe Hermann wrote:
Hi,
here's a patch for the Neoware Eon 4000s thin client, based on the info from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html
Looks nice. I wonder whether we really want this stuff to depend on ROMCC.
On the long run: no. But that's for another patch (and requires lots more work).
Does CAR work for the GX1?
Not yet, but it's possible to do. I think Juergen Beisert (CC'd) wrote something for GX1 in v3 a while ago (?) Juergen, do you still have that code and will it work for v3 (and even better, also for v2)? If so, please post it with a Signed-off-by so we can get it into svn.
The code still exists. But I have no idea how I should add it to v2. I do not know how CAR in v2 works.
Juergen
Hi Jürgen,
On 13.07.2008 21:37, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Uwe Hermann wrote:
On Fri, Jul 11, 2008 at 11:17:53PM +0200, Carl-Daniel Hailfinger wrote:
Does CAR work for the GX1?
Not yet, but it's possible to do. I think Juergen Beisert (CC'd) wrote something for GX1 in v3 a while ago (?) Juergen, do you still have that code and will it work for v3 (and even better, also for v2)? If so, please post it with a Signed-off-by so we can get it into svn.
The code still exists. But I have no idea how I should add it to v2. I do not know how CAR in v2 works.
Can you just post the code to the list? Then we can review it and commit.
Regards, Carl-Daniel
Hi Carl-Daniel,
On Sonntag, 13. Juli 2008, Carl-Daniel Hailfinger wrote:
On 13.07.2008 21:37, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Uwe Hermann wrote:
On Fri, Jul 11, 2008 at 11:17:53PM +0200, Carl-Daniel Hailfinger wrote:
Does CAR work for the GX1?
Not yet, but it's possible to do. I think Juergen Beisert (CC'd) wrote something for GX1 in v3 a while ago (?) Juergen, do you still have that code and will it work for v3 (and even better, also for v2)? If so, please post it with a Signed-off-by so we can get it into svn.
The code still exists. But I have no idea how I should add it to v2. I do not know how CAR in v2 works.
Can you just post the code to the list? Then we can review it and commit.
Regards, Carl-Daniel
Its not adapted to v2 nor v3. Its only an example, how to do it for CPUs with these special cache test registers (like older i486 and the Geode GX1).
After running this program, you have (a very fast) RAM at physical address __car_data_dst up to (__car_data_dst + __car_size). These two symbols are generated by my linker script. I'm using this code in my current u-boot-v2 development for ia32.
Note: This code must run with *disabled* cache and this piece of RAM only exists and is useable, _until_you_enable_the_cache_! Note also: You should locate this CAR area in the regular SDRAM area, because when you enable the cache (after SDRAM controller initialisation), the cache unit will flush its content to the SDRAM. It will fail badly if at the same physical address is no real memory to write/flush to.
/** * This maps the cache with the help of the cache debug and test registers * * Mapping of the cache happens from __car_data_dst as startaddress * up to (__car_data_dst + __car_size) as endaddress * * __car_data_dst contains *target's* physical CAR start address of * the CAR area, __car_size the size of the whole CAR area (in bytes) */ .code32 .section ".flat_mode", "ax" .extern pre_c_stage .extern __car_data_dst .extern __car_size .globl cache_as_ram
cache_as_ram: movl %eax, %ebp /* Save the BIST value */
movl $__car_data_dst, %edi movl $__car_size, %ecx
next_cache_line: movl $0xdeadbeef, %eax
/* Fill up cache fill buffer (one cache line = 16 bytes) */ movl %ebx, %ebx movl %ebx, %tr5 /* entry 0 */ movl %eax, %tr3
addb $0x04, %bl movl %ebx, %tr5 /* entry 1 */ movl %eax, %tr3
addb $0x04, %bl movl %ebx, %tr5 /* entry 2 */ movl %eax, %tr3
addb $0x04, %bl movl %ebx, %tr5 /* entry 3 */ movl %eax, %tr3
/* map this line to a fixed address */ movl %edi, %eax andl $0xFFFFF000, %eax orb $0x04, %ah movl %eax, %tr4
/* select correct set and line now */
/* calculate cache line from physical address bit [11:4] */ movl %edi, %eax andl $0x00000FF0, %eax
/* calculate cache set from physical address bit [13:12] */ movl %edi, %ebx andl $0x00003000, %ebx shrl $0xA, %ebx
orl %ebx, %eax orb $0x01, %al /* write buffer command */
movl %eax, %tr5 /* do it */
/* loop until full cache is mapped */ addl $0x10, %edi subl $0x10, %ecx jnz next_cache_line
movl %ebp, %eax /* Restore the BIST value */
jmp pre_c_stage /* prepare to run C code */
/* * When the standard system RAM is up and running we can switch the cache into * its native mode. There is nothing special to do here, as the cache is * currently fully initialised. Each line has its dirty bit set, so regular * use of cache can start immediately. */ .globl disable_cache_as_ram
disable_cache_as_ram: movl %cr0, %eax andl $0x9fffffff,%eax movl %eax, %cr0 ret
Regards Juergen
Hi Jürgen,
thanks a lot for the code.
On 13.07.2008 22:50, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Carl-Daniel Hailfinger wrote:
On 13.07.2008 21:37, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Uwe Hermann wrote:
On Fri, Jul 11, 2008 at 11:17:53PM +0200, Carl-Daniel Hailfinger wrote:
Does CAR work for the GX1?
Not yet, but it's possible to do. I think Juergen Beisert (CC'd) wrote something for GX1 in v3 a while ago (?) Juergen, do you still have that code and will it work for v3 (and even better, also for v2)? If so, please post it with a Signed-off-by so we can get it into svn.
The code still exists. But I have no idea how I should add it to v2. I do not know how CAR in v2 works.
Can you just post the code to the list? Then we can review it and commit.
Its not adapted to v2 nor v3. Its only an example, how to do it for CPUs with these special cache test registers (like older i486 and the Geode GX1).
You say "older i486". Does that mean newer i486 have different registers?
After running this program, you have (a very fast) RAM at physical address __car_data_dst up to (__car_data_dst + __car_size). These two symbols are generated by my linker script. I'm using this code in my current u-boot-v2 development for ia32.
Note: This code must run with *disabled* cache and this piece of RAM only exists and is useable, _until_you_enable_the_cache_! Note also: You should locate this CAR area in the regular SDRAM area, because when you enable the cache (after SDRAM controller initialisation), the cache unit will flush its content to the SDRAM. It will fail badly if at the same physical address is no real memory to write/flush to.
Hm. I thought a self-copy followed by a WBINVD was required to transfer the cache contents to the SDRAM. Our GeodeLX CAR disable function basically looks like this: setup_RCONF setup_GLIU0 setup_GLIU1 __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); __asm__ __volatile__ ("wbinvd\n");
Regards, Carl-Daniel
Hi Carl-Daniel,
On Montag, 14. Juli 2008, Carl-Daniel Hailfinger wrote:
thanks a lot for the code.
On 13.07.2008 22:50, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Carl-Daniel Hailfinger wrote:
On 13.07.2008 21:37, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Uwe Hermann wrote:
On Fri, Jul 11, 2008 at 11:17:53PM +0200, Carl-Daniel Hailfinger wrote:
Does CAR work for the GX1?
Not yet, but it's possible to do. I think Juergen Beisert (CC'd) wrote something for GX1 in v3 a while ago (?) Juergen, do you still have that code and will it work for v3 (and even better, also for v2)? If so, please post it with a Signed-off-by so we can get it into svn.
The code still exists. But I have no idea how I should add it to v2. I do not know how CAR in v2 works.
Can you just post the code to the list? Then we can review it and commit.
Its not adapted to v2 nor v3. Its only an example, how to do it for CPUs with these special cache test registers (like older i486 and the Geode GX1).
You say "older i486". Does that mean newer i486 have different registers?
No, that's not what I mean. All i486 are "old", aren't they? ;-) My amd486 datasheet tells me, this CPU has such registers. I believe the old Intel i486s also have such registers (but I'm not sure).
After running this program, you have (a very fast) RAM at physical address __car_data_dst up to (__car_data_dst + __car_size). These two symbols are generated by my linker script. I'm using this code in my current u-boot-v2 development for ia32.
Note: This code must run with *disabled* cache and this piece of RAM only exists and is useable, _until_you_enable_the_cache_! Note also: You should locate this CAR area in the regular SDRAM area, because when you enable the cache (after SDRAM controller initialisation), the cache unit will flush its content to the SDRAM. It will fail badly if at the same physical address is no real memory to write/flush to.
Hm. I thought a self-copy followed by a WBINVD was required to transfer the cache contents to the SDRAM.
But also the WBINVD will fail, if at the physical mapping address is no valid device (like SDRAM or PCI...). In this case you must use the INVD instruction instead. But I believe you know what you are doing ;-)
Juergen
Hi Jürgen,
On 14.07.2008 10:21, Juergen Beisert wrote:
Hi Carl-Daniel,
On Montag, 14. Juli 2008, Carl-Daniel Hailfinger wrote:
thanks a lot for the code.
On 13.07.2008 22:50, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Carl-Daniel Hailfinger wrote:
[CAR for GX1]
Its not adapted to v2 nor v3. Its only an example, how to do it for CPUs with these special cache test registers (like older i486 and the Geode GX1).
You say "older i486". Does that mean newer i486 have different registers?
No, that's not what I mean. All i486 are "old", aren't they? ;-) My amd486 datasheet tells me, this CPU has such registers. I believe the old Intel i486s also have such registers (but I'm not sure).
Thanks for clarifying.
After running this program, you have (a very fast) RAM at physical address __car_data_dst up to (__car_data_dst + __car_size). These two symbols are generated by my linker script. I'm using this code in my current u-boot-v2 development for ia32.
Note: This code must run with *disabled* cache and this piece of RAM only exists and is useable, _until_you_enable_the_cache_! Note also: You should locate this CAR area in the regular SDRAM area, because when you enable the cache (after SDRAM controller initialisation), the cache unit will flush its content to the SDRAM. It will fail badly if at the same physical address is no real memory to write/flush to.
Hm. I thought a self-copy followed by a WBINVD was required to transfer the cache contents to the SDRAM.
But also the WBINVD will fail, if at the physical mapping address is no valid device (like SDRAM or PCI...). In this case you must use the INVD instruction instead. But I believe you know what you are doing ;-)
Yes, my question was mostly about the lack of WBINVD in your code. Having a CAR area not backed by SDRAM would be "interesting", not to say stupid in our case.
I think I have figured out where to merge your code into the existing Geode LX CAR code.
Regards, Carl-Daniel
Hi Carl-Daniel,
On Montag, 14. Juli 2008, Carl-Daniel Hailfinger wrote:
On 14.07.2008 10:21, Juergen Beisert wrote:
Hi Carl-Daniel,
On Montag, 14. Juli 2008, Carl-Daniel Hailfinger wrote:
thanks a lot for the code.
On 13.07.2008 22:50, Juergen Beisert wrote:
On Sonntag, 13. Juli 2008, Carl-Daniel Hailfinger wrote:
[CAR for GX1]
Its not adapted to v2 nor v3. Its only an example, how to do it for CPUs with these special cache test registers (like older i486 and the Geode GX1).
You say "older i486". Does that mean newer i486 have different registers?
No, that's not what I mean. All i486 are "old", aren't they? ;-) My amd486 datasheet tells me, this CPU has such registers. I believe the old Intel i486s also have such registers (but I'm not sure).
Thanks for clarifying.
After running this program, you have (a very fast) RAM at physical address __car_data_dst up to (__car_data_dst + __car_size). These two symbols are generated by my linker script. I'm using this code in my current u-boot-v2 development for ia32.
Note: This code must run with *disabled* cache and this piece of RAM only exists and is useable, _until_you_enable_the_cache_! Note also: You should locate this CAR area in the regular SDRAM area, because when you enable the cache (after SDRAM controller initialisation), the cache unit will flush its content to the SDRAM. It will fail badly if at the same physical address is no real memory to write/flush to.
Hm. I thought a self-copy followed by a WBINVD was required to transfer the cache contents to the SDRAM.
But also the WBINVD will fail, if at the physical mapping address is no valid device (like SDRAM or PCI...). In this case you must use the INVD instruction instead. But I believe you know what you are doing ;-)
Yes, my question was mostly about the lack of WBINVD in your code. Having a CAR area not backed by SDRAM would be "interesting", not to say stupid in our case.
I think I have figured out where to merge your code into the existing Geode LX CAR code.
The Geode LX lacks these cache test registers! Only the GX1 supports them.
Juergen
On 14.07.2008 11:59, Juergen Beisert wrote:
Hi Carl-Daniel,
On Montag, 14. Juli 2008, Carl-Daniel Hailfinger wrote:
I think I have figured out where to merge your code into the existing Geode LX CAR code.
The Geode LX lacks these cache test registers! Only the GX1 supports them.
Let me reword this: We currently perform some early processor init, the switch to protected mode and other stuff in one big file. The "merge" is more like cutting out the LX code and replacing it with your cache test code in that file, then storing the result in a new file.
Regards, Carl-Daniel
On Mon, Jul 14, 2008 at 10:55:03AM +0200, Carl-Daniel Hailfinger wrote:
I think I have figured out where to merge your code into the existing Geode LX CAR code.
Is it really a good idea to have the same stage0 for GX1 and LX?
//Peter
On Thu, Jul 10, 2008 at 01:55:31PM +0200, Uwe Hermann wrote:
Hi,
here's a patch for the Neoware Eon 4000s thin client, based on the info from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html
*ping*
Can I get an Acked-by for this so we can commit a new board? It's been tested to work on hardware with 'irqpoll', might need some more investigations to fixup IRQs so it'll also work without 'irqpoll', but this is definately committable IMHO.
Thanks, Uwe.
http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Initia support for the ASI MB-5BLGP (Neoware Eon 4000s).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de
Index: src/mainboard/asi/mb_5blgp/Config.lb
--- src/mainboard/asi/mb_5blgp/Config.lb (Revision 0) +++ src/mainboard/asi/mb_5blgp/Config.lb (Revision 0) @@ -0,0 +1,137 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
+end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
+ ROM_SECTION_OFFSET + 1)+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE
- object irq_tables.o
+end +makerule ./failover.E
- depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end +makerule ./failover.inc
- depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end +makerule ./auto.E
- # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- depends "$(MAINBOARD)/auto.c ./romcc"
- action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end +makerule ./auto.inc
- # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- depends "$(MAINBOARD)/auto.c ./romcc"
- action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
+else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
+end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
+end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc
+dir /pc80 +config chip.h
+chip northbridge/amd/gx1 # Northbridge
- device pci_domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- chip southbridge/amd/cs5530 # Southbridge
device pci 0f.0 on end # Ethernetdevice pci 12.0 on # ISA bridgechip superio/nsc/pc87351 # Super I/Odevice pnp 2e.0 off # Floppyio 0x60 = 0x3f0irq 0x70 = 6drq 0x74 = 2enddevice pnp 2e.1 on # Parallel portio 0x60 = 0x378irq 0x70 = 7enddevice pnp 2e.2 on # COM2io 0x60 = 0x2f8irq 0x70 = 3enddevice pnp 2e.e on # COM1io 0x60 = 0x3f8irq 0x70 = 4enddevice pnp 2e.4 on # System wake-up control (SWC)irq 0x60 = 0x500enddevice pnp 2e.5 on # PS/2 mouseirq 0x70 = 12enddevice pnp 2e.6 on # PS/2 keyboardio 0x60 = 0x60io 0x62 = 0x64irq 0x70 = 1enddevice pnp 2e.7 on # GPIOirq 0x60 = 0x800enddevice pnp 2e.8 on # Fan speed controlirq 0x60 = 0x900endendenddevice pci 12.1 off end # SMIdevice pci 12.2 on end # IDEdevice pci 12.3 on end # Audiodevice pci 12.4 on end # VGAdevice pci 13.0 on end # USBregister "ide0_enable" = "1"register "ide1_enable" = "0" # No connector on this board- end
- end
- chip cpu/amd/model_gx1 # CPU
- end
+end Index: src/mainboard/asi/mb_5blgp/irq_tables.c =================================================================== --- src/mainboard/asi/mb_5blgp/irq_tables.c (Revision 0) +++ src/mainboard/asi/mb_5blgp/irq_tables.c (Revision 0) @@ -0,0 +1,46 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+#include <arch/pirq_routing.h>
+const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x12 << 3) | 0x0, /* Interrupt router device */
- 0x8800, /* IRQs devoted exclusively to PCI usage */
- 0x1078, /* Vendor */
- 0x2, /* Device */
- 0, /* Crap (miniport) */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x96, /* Checksum */
- {
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */{0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */{0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */- }
+};
+unsigned long write_pirq_routing_table(unsigned long addr) +{
- return copy_pirq_routing_table(addr);
+} Index: src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- src/mainboard/asi/mb_5blgp/Options.lb (Revision 0) +++ src/mainboard/asi/mb_5blgp/Options.lb (Revision 0) @@ -0,0 +1,105 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_VIDEO_MB +uses CONFIG_SPLASH_GRAPHIC +uses CONFIG_GX1_VIDEO +uses CONFIG_GX1_VIDEOMODE +uses PIRQ_ROUTE
+## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +default CONFIG_GX1_VIDEO = 1 +default CONFIG_GX1_VIDEOMODE = 0 +default CONFIG_SPLASH_GRAPHIC = 1 +default CONFIG_VIDEO_MB = 2
+default ROM_SIZE = 256 * 1024 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default PIRQ_ROUTE = 1 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_OPTION_TABLE = 0 +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc " +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9
+end Index: src/mainboard/asi/mb_5blgp/auto.c =================================================================== --- src/mainboard/asi/mb_5blgp/auto.c (Revision 0) +++ src/mainboard/asi/mb_5blgp/auto.c (Revision 0) @@ -0,0 +1,45 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+#define ASSEMBLY 1
+#include <stdint.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/gx1/raminit.c" +#include "cpu/x86/bist.h" +#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
+static void main(unsigned long bist) +{
- pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
- report_bist_failure(bist);
- sdram_init();
- /* ram_check(0, 640 * 1024); */
+} Index: src/mainboard/asi/mb_5blgp/chip.h =================================================================== --- src/mainboard/asi/mb_5blgp/chip.h (Revision 0) +++ src/mainboard/asi/mb_5blgp/chip.h (Revision 0) @@ -0,0 +1,22 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+extern struct chip_operations mainboard_asi_mb_5blgp_ops; +struct mainboard_asi_mb_5blgp_config {}; Index: src/mainboard/asi/mb_5blgp/mainboard.c =================================================================== --- src/mainboard/asi/mb_5blgp/mainboard.c (Revision 0) +++ src/mainboard/asi/mb_5blgp/mainboard.c (Revision 0) @@ -0,0 +1,26 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+#include <device/device.h> +#include "chip.h"
+struct chip_operations mainboard_asi_mb_5blgp_ops = {
- CHIP_NAME("ASI MB-5BLGP Mainboard")
+}; Index: targets/asi/mb_5blgp/Config.lb =================================================================== --- targets/asi/mb_5blgp/Config.lb (Revision 0) +++ targets/asi/mb_5blgp/Config.lb (Revision 0) @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+target mb_5blgp +mainboard asi/mb_5blgp
+option ROM_SIZE = 256 * 1024
+option MAINBOARD_VENDOR = "ASI" +option MAINBOARD_PART_NUMBER = "MB-5BLGP"
+option IRQ_SLOT_COUNT = 3
+## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +option CONFIG_GX1_VIDEO = 1 +option CONFIG_GX1_VIDEOMODE = 0 +option CONFIG_SPLASH_GRAPHIC = 1 +option CONFIG_VIDEO_MB = 2
+option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9
+romimage "normal"
- option USE_FALLBACK_IMAGE = 0
- option COREBOOT_EXTRA_VERSION = ".0Normal"
- payload ../payload.elf
+end
+romimage "fallback"
- option USE_FALLBACK_IMAGE = 1
- option COREBOOT_EXTRA_VERSION = ".0Fallback"
- payload ../payload.elf
+end
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
-- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On 03.08.2008 22:57, Uwe Hermann wrote:
On Thu, Jul 10, 2008 at 01:55:31PM +0200, Uwe Hermann wrote:
Hi,
here's a patch for the Neoware Eon 4000s thin client, based on the info from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html
*ping*
Can I get an Acked-by for this so we can commit a new board? It's been tested to work on hardware with 'irqpoll', might need some more investigations to fixup IRQs so it'll also work without 'irqpoll', but this is definately committable IMHO.
If you fix the typo in the commit message (InitiaL): Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
Initia support for the ASI MB-5BLGP (Neoware Eon 4000s).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de
Index: src/mainboard/asi/mb_5blgp/Config.lb
--- src/mainboard/asi/mb_5blgp/Config.lb (Revision 0) +++ src/mainboard/asi/mb_5blgp/Config.lb (Revision 0) @@ -0,0 +1,137 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
+end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
+ ROM_SECTION_OFFSET + 1)+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE
- object irq_tables.o
+end +makerule ./failover.E
- depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end +makerule ./failover.inc
- depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end +makerule ./auto.E
- # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- depends "$(MAINBOARD)/auto.c ./romcc"
- action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end +makerule ./auto.inc
- # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- depends "$(MAINBOARD)/auto.c ./romcc"
- action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
+else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
+end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
+end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc
+dir /pc80 +config chip.h
+chip northbridge/amd/gx1 # Northbridge
- device pci_domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- chip southbridge/amd/cs5530 # Southbridge
device pci 0f.0 on end # Ethernetdevice pci 12.0 on # ISA bridgechip superio/nsc/pc87351 # Super I/Odevice pnp 2e.0 off # Floppyio 0x60 = 0x3f0irq 0x70 = 6drq 0x74 = 2enddevice pnp 2e.1 on # Parallel portio 0x60 = 0x378irq 0x70 = 7enddevice pnp 2e.2 on # COM2io 0x60 = 0x2f8irq 0x70 = 3enddevice pnp 2e.e on # COM1io 0x60 = 0x3f8irq 0x70 = 4enddevice pnp 2e.4 on # System wake-up control (SWC)irq 0x60 = 0x500enddevice pnp 2e.5 on # PS/2 mouseirq 0x70 = 12enddevice pnp 2e.6 on # PS/2 keyboardio 0x60 = 0x60io 0x62 = 0x64irq 0x70 = 1enddevice pnp 2e.7 on # GPIOirq 0x60 = 0x800enddevice pnp 2e.8 on # Fan speed controlirq 0x60 = 0x900endendenddevice pci 12.1 off end # SMIdevice pci 12.2 on end # IDEdevice pci 12.3 on end # Audiodevice pci 12.4 on end # VGAdevice pci 13.0 on end # USBregister "ide0_enable" = "1"register "ide1_enable" = "0" # No connector on this board- end
- end
- chip cpu/amd/model_gx1 # CPU
- end
+end Index: src/mainboard/asi/mb_5blgp/irq_tables.c =================================================================== --- src/mainboard/asi/mb_5blgp/irq_tables.c (Revision 0) +++ src/mainboard/asi/mb_5blgp/irq_tables.c (Revision 0) @@ -0,0 +1,46 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+#include <arch/pirq_routing.h>
+const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x12 << 3) | 0x0, /* Interrupt router device */
- 0x8800, /* IRQs devoted exclusively to PCI usage */
- 0x1078, /* Vendor */
- 0x2, /* Device */
- 0, /* Crap (miniport) */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x96, /* Checksum */
- {
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */{0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */{0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */- }
+};
+unsigned long write_pirq_routing_table(unsigned long addr) +{
- return copy_pirq_routing_table(addr);
+} Index: src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- src/mainboard/asi/mb_5blgp/Options.lb (Revision 0) +++ src/mainboard/asi/mb_5blgp/Options.lb (Revision 0) @@ -0,0 +1,105 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_VIDEO_MB +uses CONFIG_SPLASH_GRAPHIC +uses CONFIG_GX1_VIDEO +uses CONFIG_GX1_VIDEOMODE +uses PIRQ_ROUTE
+## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +default CONFIG_GX1_VIDEO = 1 +default CONFIG_GX1_VIDEOMODE = 0 +default CONFIG_SPLASH_GRAPHIC = 1 +default CONFIG_VIDEO_MB = 2
+default ROM_SIZE = 256 * 1024 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default PIRQ_ROUTE = 1 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_OPTION_TABLE = 0 +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc " +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9
+end Index: src/mainboard/asi/mb_5blgp/auto.c =================================================================== --- src/mainboard/asi/mb_5blgp/auto.c (Revision 0) +++ src/mainboard/asi/mb_5blgp/auto.c (Revision 0) @@ -0,0 +1,45 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+#define ASSEMBLY 1
+#include <stdint.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/gx1/raminit.c" +#include "cpu/x86/bist.h" +#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
+static void main(unsigned long bist) +{
- pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
- report_bist_failure(bist);
- sdram_init();
- /* ram_check(0, 640 * 1024); */
+} Index: src/mainboard/asi/mb_5blgp/chip.h =================================================================== --- src/mainboard/asi/mb_5blgp/chip.h (Revision 0) +++ src/mainboard/asi/mb_5blgp/chip.h (Revision 0) @@ -0,0 +1,22 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+extern struct chip_operations mainboard_asi_mb_5blgp_ops; +struct mainboard_asi_mb_5blgp_config {}; Index: src/mainboard/asi/mb_5blgp/mainboard.c =================================================================== --- src/mainboard/asi/mb_5blgp/mainboard.c (Revision 0) +++ src/mainboard/asi/mb_5blgp/mainboard.c (Revision 0) @@ -0,0 +1,26 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+#include <device/device.h> +#include "chip.h"
+struct chip_operations mainboard_asi_mb_5blgp_ops = {
- CHIP_NAME("ASI MB-5BLGP Mainboard")
+}; Index: targets/asi/mb_5blgp/Config.lb =================================================================== --- targets/asi/mb_5blgp/Config.lb (Revision 0) +++ targets/asi/mb_5blgp/Config.lb (Revision 0) @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann uwe@hermann-uwe.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+target mb_5blgp +mainboard asi/mb_5blgp
+option ROM_SIZE = 256 * 1024
+option MAINBOARD_VENDOR = "ASI" +option MAINBOARD_PART_NUMBER = "MB-5BLGP"
+option IRQ_SLOT_COUNT = 3
+## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +option CONFIG_GX1_VIDEO = 1 +option CONFIG_GX1_VIDEOMODE = 0 +option CONFIG_SPLASH_GRAPHIC = 1 +option CONFIG_VIDEO_MB = 2
+option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9
+romimage "normal"
- option USE_FALLBACK_IMAGE = 0
- option COREBOOT_EXTRA_VERSION = ".0Normal"
- payload ../payload.elf
+end
+romimage "fallback"
- option USE_FALLBACK_IMAGE = 1
- option COREBOOT_EXTRA_VERSION = ".0Fallback"
- payload ../payload.elf
+end
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
-- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On Sun, Aug 03, 2008 at 11:12:18PM +0200, Carl-Daniel Hailfinger wrote:
If you fix the typo in the commit message (InitiaL): Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Thanks, r3469.
Uwe.
-
Carl-Daniel Hailfinger -
Juergen Beisert -
Peter Stuge -
Uwe Hermann