Re: [coreboot] Coreboot hangs during SYS_RESET

[Naresh G. Solanki]

1. Can you make sure right microcode based on the CPUID is added. This is
must. Based on CPUID(I guess 506cX for APL), you can locate them at
3rdparty/blobs/..
Select CBFS GENERATE and specify CPU UCODE BINARIES path.

2. Can you provide complete log and config(after adding microcode into
cbfs) if you still see sys_reset issue.

Regards,
Naresh

On Wed 7 Nov, 2018, 8:56 PM Aaron Durbin via coreboot <[e-mail]
wrote:
> On Wed, Nov 7, 2018 at 6:47 AM Antony AbeePrakash X V
>  wrote:
> > Hi,
> >
> > We are developing coreboot (with Intel FSP) for apollo lake platform
>
> custom board. We are facing a hang issue during the SYS_RESET button press.
> > Observations:
> >
> > With soft reset the board gets hang(occurs within 2 or 3 reboot) with
>
> POST code 0x38 and the coreboot log stops during the romstage relocation.
> (Logs attached for Ref.)
> > When the SYS_RESET is pressed again the board boots and hangs at same
>
> POST code 0x38.
> > Please provide feedback and help us to resolve this issue.
>
> I'm confused by the following logs in romstage:
>
> CBFS @ 0 size 70000
> CBFS: Locating 'romstage.rel'
> CBFS: Found @ offset 64c0 size 480
> romstage is relocated from fef40054 to 0x7abf1000
>
> I'm not familiar where this code is coming from.  Are you carrying
> external patches or have I forgotten what is going on here?
> > Currently our coreboot build does not include any microcode
>
> (CPU_MICROCODE_CBFS_NONE). We tried to change it as “Generate from tree” in
> memuconfig.
> > But the build fails with fatal error saying no microcode/microcode.h
>
> file.
> > Whether the CPU by default have microcode ? or we need to build the
>
> microcode in coreboot ?
> > Please advise on this.
> >
> > Thanks & Regards,
> >
> > Antony
> >
> > L&T Technology Services Ltd
> >
> > www.LntTechservices.com
> >
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