[commit] r6464 - in trunk/src: cpu/amd cpu/amd/model_10xxx cpu/amd/socket_C32 northbridge/amd/amdfam10 northbridge/amd/amdmct northbridge/amd/amdmct/mct
Author: zbao Date: Mon Mar 28 06:29:14 2011 New Revision: 6464 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6464
Log: Add AMD C32 support. It is based on other existing Fam10 code.
Signed-off-by: Zheng Bao zheng.bao@amd.com Acked-by: Marc Jones marcj303@gmail.com
Added: trunk/src/cpu/amd/model_10xxx/mc_patch_010000c4.h trunk/src/cpu/amd/socket_C32/ (props changed) - copied from r6462, trunk/src/cpu/amd/socket_AM3/ trunk/src/cpu/amd/socket_C32/socket_C32.c (contents, props changed) - copied, changed from r6462, trunk/src/cpu/amd/socket_AM3/socket_AM3.c Deleted: trunk/src/cpu/amd/socket_C32/socket_AM3.c Modified: trunk/src/cpu/amd/Kconfig trunk/src/cpu/amd/Makefile.inc trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c trunk/src/cpu/amd/model_10xxx/processor_name.c trunk/src/cpu/amd/model_10xxx/update_microcode.c trunk/src/cpu/amd/socket_C32/Kconfig trunk/src/cpu/amd/socket_C32/Makefile.inc trunk/src/cpu/amd/socket_C32/chip.h trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdmct/amddefs.h trunk/src/northbridge/amd/amdmct/mct/mct_d.c
Modified: trunk/src/cpu/amd/Kconfig ============================================================================== --- trunk/src/cpu/amd/Kconfig Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/Kconfig Mon Mar 28 06:29:14 2011 (r6464) @@ -8,6 +8,7 @@ source src/cpu/amd/socket_AM2/Kconfig source src/cpu/amd/socket_AM2r2/Kconfig source src/cpu/amd/socket_AM3/Kconfig +source src/cpu/amd/socket_C32/Kconfig source src/cpu/amd/socket_ASB2/Kconfig source src/cpu/amd/socket_F/Kconfig source src/cpu/amd/socket_F_1207/Kconfig
Modified: trunk/src/cpu/amd/Makefile.inc ============================================================================== --- trunk/src/cpu/amd/Makefile.inc Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/Makefile.inc Mon Mar 28 06:29:14 2011 (r6464) @@ -7,6 +7,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2 +subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32 subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 subdirs-$(CONFIG_CPU_AMD_LX) += model_lx
Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Mon Mar 28 06:29:14 2011 (r6464) @@ -89,9 +89,25 @@ 0x00000000, 1 << (33-32), 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
- { BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL, + { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL, 0x00000000, 1 << (35-32), 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */ + + { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00000004, 0x00000000, + 0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */ + + { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC, + 0x0000000C, 0x00000000, + 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */ + + { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00000000, 1 << (50-32), + 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/ + + { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00000000, 1 << (51 - 32), + 0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */ };
@@ -140,28 +156,28 @@ * program Link Global Extended Control Register[ForceFullT0] * (F0x16C[15:13]) to 000b */
- { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */ + { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */ 0x00000000, 0x00000100 }, - { 0, 0x174, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x178, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x17C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x180, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x184, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x188, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x18C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 },
/* Link Global Extended Control Register */ - { 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, - 0x00000014, 0x0000E03F }, /* [15:13] ForceFullT0 = 0b, + { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b, * Set T0Time 14h per BKDG */
@@ -297,7 +313,7 @@ [5] DisPciCfgCpuMstAbtRsp = 1, [1] SyncFloodOnUsPwDataErr = 1 */
- /* errata 346 - Fam10 C2 -- FIXME at 25.6.2010 should apply to BL-C[23] too but I can't find their constants + /* errata 346 - Fam10 C2, C3 * System software should set F3x188[22] to 1b. */ { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL, 0x00400000, 0x00400000 }, @@ -324,100 +340,100 @@ u32 mask; } fam10_htphy_default[] = {
- /* Errata 344 - Fam10 C2/D0 -- FIXME at 25.6.2010 should be for ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them + /* Errata 344 - Fam10 C2/C3, D0/D1 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ - { 0x60, AMD_DRBH_Cx , AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 },
- { 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 },
- /* Errata 354 - Fam10 C2 - FIXME at 25.6.2010 affects RB-C2, BL-C2,DA-C2,RB-C3,BL-C3,DA-C3, but BL-C[23] have no constants + /* Errata 354 - Fam10 C2, C3 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ - { 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 },
- { 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 },
- /* Errata 327 - Fam10 C2/D0 + /* Errata 327 - Fam10 C2/C3, D0/D1 * BIOS should set the Link Phy Impedance Register[RttCtl] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and * Link Phy Impedance Register[RttIndex] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ - { 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 },
- { 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
- { 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
{ 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Added: trunk/src/cpu/amd/model_10xxx/mc_patch_010000c4.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/model_10xxx/mc_patch_010000c4.h Mon Mar 28 06:29:14 2011 (r6464) @@ -0,0 +1,186 @@ +/* + ****************************************************************************** + * + * Copyright 2010 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +0x10, 0x20, 0x03, 0x03, 0xc4, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x01, +0x4a, 0xe0, 0x9c, 0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x81, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xa7, 0x0b, 0x00, 0x00, +0x14, 0x0c, 0x00, 0x00, 0x55, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +0x51, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0x4f, 0xdf, 0x38, 0x00, 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Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Mon Mar 28 06:29:14 2011 (r6464) @@ -145,6 +145,7 @@ { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ { 0, 0 }, };
Modified: trunk/src/cpu/amd/model_10xxx/processor_name.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/processor_name.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/model_10xxx/processor_name.c Mon Mar 28 06:29:14 2011 (r6464) @@ -154,6 +154,25 @@ {0, 0, 0, NULL} };
+static const struct str_s String1_socket_C32[] = { + {0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"}, + {0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"}, + {0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "}, + {0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "}, + {0, 0, 0, NULL} +}; + +static const struct str_s String2_socket_C32[] = { + {0x00, 0x03, 0x00, " HE"}, + {0x00, 0x03, 0x01, " EE"}, + {0x00, 0x05, 0x00, " HE"}, + {0x00, 0x05, 0x01, " EE"}, + {0x01, 0x03, 0x01, "QS HE"}, + {0x01, 0x03, 0x02, "LE HE"}, + {0x01, 0x05, 0x01, "KX HE"}, + {0x01, 0x05, 0x02, "GL EE"}, + {0, 0, 0, NULL} +};
const char const *unknown = "AMD Processor model unknown"; const char const *unknown2 = " type unknown"; @@ -218,6 +237,10 @@ str = String1_socket_AM2; str2 = String2_socket_AM2; break; + case 5: /* C32 */ + str = String1_socket_C32; + str2 = String2_socket_C32; + break; default: goto done; }
Modified: trunk/src/cpu/amd/model_10xxx/update_microcode.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/update_microcode.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/model_10xxx/update_microcode.c Mon Mar 28 06:29:14 2011 (r6464) @@ -50,6 +50,7 @@ * 00100F43h (RB-C3) 1043h 010000b6h * 00100F62h (DA-C2) 1062h 0100009Fh * 00100F63h (DA-C3) 1043h 010000b6h + * 00100F81h (HY-D1) 1081h 010000c4h */
#include CONFIG_AMD_UCODE_PATCH_FILE @@ -76,6 +77,7 @@ 0x100f43, 0x1043, 0x100f62, 0x1062, 0x100f63, 0x1043, + 0x100f81, 0x1081, };
u32 new_id;
Modified: trunk/src/cpu/amd/socket_C32/Kconfig ============================================================================== --- trunk/src/cpu/amd/socket_AM3/Kconfig Sun Mar 27 18:39:58 2011 (r6462) +++ trunk/src/cpu/amd/socket_C32/Kconfig Mon Mar 28 06:29:14 2011 (r6464) @@ -1,4 +1,4 @@ -config CPU_AMD_SOCKET_AM3 +config CPU_AMD_SOCKET_C32 bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT @@ -7,36 +7,36 @@
config CPU_SOCKET_TYPE hex - default 0x11 - depends on CPU_AMD_SOCKET_AM3 + default 0x14 + depends on CPU_AMD_SOCKET_C32
config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32
config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32
config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32
config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32
config XIP_ROM_BASE hex default 0xfff80000 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32
config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32
Modified: trunk/src/cpu/amd/socket_C32/Makefile.inc ============================================================================== --- trunk/src/cpu/amd/socket_AM3/Makefile.inc Sun Mar 27 18:39:58 2011 (r6462) +++ trunk/src/cpu/amd/socket_C32/Makefile.inc Mon Mar 28 06:29:14 2011 (r6464) @@ -1,4 +1,4 @@ -ramstage-y += socket_AM3.c +ramstage-y += socket_C32.c subdirs-y += ../model_10xxx subdirs-y += ../quadcore subdirs-y += ../mtrr
Modified: trunk/src/cpu/amd/socket_C32/chip.h ============================================================================== --- trunk/src/cpu/amd/socket_AM3/chip.h Sun Mar 27 18:39:58 2011 (r6462) +++ trunk/src/cpu/amd/socket_C32/chip.h Mon Mar 28 06:29:14 2011 (r6464) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-extern struct chip_operations cpu_amd_socket_AM3_ops; +extern struct chip_operations cpu_amd_socket_C32_ops;
-struct cpu_amd_socket_AM3_config { +struct cpu_amd_socket_C32_config { };
Copied and modified: trunk/src/cpu/amd/socket_C32/socket_C32.c (from r6462, trunk/src/cpu/amd/socket_AM3/socket_AM3.c) ============================================================================== --- trunk/src/cpu/amd/socket_AM3/socket_AM3.c Sun Mar 27 18:39:58 2011 (r6462, copy source) +++ trunk/src/cpu/amd/socket_C32/socket_C32.c Mon Mar 28 06:29:14 2011 (r6464) @@ -20,6 +20,6 @@ #include <device/device.h> #include "chip.h"
-struct chip_operations cpu_amd_socket_AM3_ops = { - CHIP_NAME("socket AM3") +struct chip_operations cpu_amd_socket_C32_ops = { + CHIP_NAME("socket C32") };
Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Mar 28 06:29:14 2011 (r6464) @@ -78,6 +78,9 @@ #elif CONFIG_CPU_SOCKET_TYPE == 0x13 //ASB2 #include "../amdmct/mct_ddr3/mctardk5.c" +//C32 +#elif CONFIG_CPU_SOCKET_TYPE == 0x14 +#include "../amdmct/mct_ddr3/mctardk5.c" #endif
#else /* DDR2 */ @@ -205,6 +208,9 @@ case 0x10080: ret = AMD_HY_D0; break; + case 0x10081: + ret = AMD_HY_D1; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n");
Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Mon Mar 28 06:29:14 2011 (r6464) @@ -45,6 +45,7 @@ #define AMD_HY_D0 0x04000000 /* Istanbul D0 */ #define AMD_RB_C3 0x08000000 /* ??? C3 */ #define AMD_DA_C3 0x10000000 /* XXXX C3 */ +#define AMD_HY_D1 0x20000000 /* Istanbul D1 */
/* * Groups - Create as many as you wish, from the above public values @@ -61,19 +62,18 @@ #define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA) #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) +#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) #define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 ) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) #define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) -#define AMD_DR_Dx (AMD_HY_D0) -#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) -#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) - -#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) -#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3) +#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1) +#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) +#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) +#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3)
/* * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE
Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Mon Mar 28 06:29:14 2011 (r6464) @@ -2407,7 +2407,7 @@ // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
/* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */ - if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) { + if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { if (pDCTstat->GangedMode) { val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); val |= 1 << DisAutoRefresh; @@ -2421,7 +2421,7 @@ * to ensure both DCTs are in sync (Erratum 278) */
- if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) { + if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { if (pDCTstat->GangedMode) { do { val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
-
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