RE: Freebios2 recovery progress...

[YhLu]

Eric,

You overwrite some lines in amd8131....

/* We have to enable MEM and Bus Master for IOAPIC */
        value = pci_read_config32(dev, 0x4);
        value |= 6;
        pci_write_config32(dev, 0x4, value);

Regards

YH

static void ioapic_enable(device_t dev)
{       
        uint32_t value;

value = pci_read_config32(dev, 0x44);
        if (dev->enabled) {
                value |= ((1 << 1) | (1 << 0));
        } else {
                value &= ~((1 << 1) | (1 << 0));
        }
        pci_write_config32(dev, 0x44, value);

/* We have to enable MEM and Bus Master for IOAPIC */
        value = pci_read_config32(dev, 0x4);
        value |= 6;
        pci_write_config32(dev, 0x4, value);
}

-----Original Message-----
From: [e-mail] [mailto:[e-mail]] 
Sent: Thursday, October 21, 2004 4:08 AM
To: LinuxBIOS
Subject: Freebios2 recovery progress...

I have managed to get another chunk of merging and bug fixing
done tonight.

I now have pci subsystem vendor and subsystem id's being set on
the arima hdama, so the board is now identifiable with lspci.

I have bumped the LinuxBIOS minor version so we can track
these changes.

All of the superio chips should not work or at least be very close
except the weird via superio/pci hybrid that I could not make sense
of.

I have changed all of the references to chip_control to chip_operations.
And fixed up the usage while I was in the neighborhood if I could clearly
see what the fix should be.  So Config.lb for most of the Opteron ports
should work, or at least be very close now.

It is time for me to break off and head home.

Eric

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Freebios2 recovery progress...

YhLu  writes:
> Eric,
>
> You overwrite some lines in amd8131....
>     /* We have to enable MEM and Bus Master for IOAPIC */
>     value = pci_read_config32(dev, 0x4);
>     value |= 6;
>     pci_write_config32(dev, 0x4, value);

Yep.

But in src/devices/pci_device.c:pci_scan_bus I added:
    	/* Architectural/System devices always need to
    	 * be bus masters.
    	 */
    	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
    		dev->command |= PCI_COMMAND_MASTER;
    	}

Which achieves the same thing in a generally less fragile way.
We still might have one or two devices that we need to hard code
the master command status for but this catches the general
case.

Basically system devices have well known interfaces so they are
likely to have a generic driver instead of a device specific driver.
So enabling them as bus masters looks safe and will fix all of
the cases I know about where this is needed.

And I checked and the bus master bit is still getting set on
the IOAPICs on the HDAMA.

But thanks good catch, this needed an explanation.

Did I mention I was just a little behind on merging my code? :)

Eric