SPI Flash debug console on H8SCM

[Fabian]

Hi everyone,

I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB. So I want to give SPI console a try. It seems to be a very new feature introduced here [1].

When I compile coreboot it fails with this warning:
warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CONSOLE_SPI_FLASH) selects BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY which has unmet direct dependencies (SPI_FLASH && BOOT_DEVICE_SPI_FLASH_RW_NOMMAP)

As written in [1] it's only tested for Skylake. How much effort is necessary to port it to my board? Are there more Information about SPI console? Or is there an other way to get log from my board?

One more question to the AMD experts: There are two motherboard models "H8SCM" and "H8SCM (Fam10)". Whats the difference?

Greetings,
Fabian

[1] https://mail.coreboot.org/pipermail/coreboot/2017-June/084538.html

[Youness Alaoui]

Hi Fabian,

It was ported to older intel architectures by Nicola Corna here :
https://review.coreboot.org/#/c/21107/
I don't know what would need to be done to port it to work with amd,
but in theory, all it needs is for the chipset to support SPI
operations. If it can read and write to the spi flash for the purposes
of the mrc.cache, then it should be easy to make it work.
The real work to port it to other architectures was pretty much only
to make sure the spi controller doesn't use global variables so it
could be included in the bootblock and romstage.

Good luck.
Youness.

On Fri, Sep 15, 2017 at 12:40 PM, Fabian  wrote:
> Hi everyone,
>
> I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB. So I want to give SPI console a try. It seems to be a very new feature introduced here [1].
>
> When I compile coreboot it fails with this warning:
> warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CONSOLE_SPI_FLASH) selects BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY which has unmet direct dependencies (SPI_FLASH && BOOT_DEVICE_SPI_FLASH_RW_NOMMAP)
>
> As written in [1] it's only tested for Skylake. How much effort is necessary to port it to my board? Are there more Information about SPI console? Or is there an other way to get log from my board?
>
> One more question to the AMD experts: There are two motherboard models "H8SCM" and "H8SCM (Fam10)". Whats the difference?
>
> Greetings,
> Fabian
>
> [1] https://mail.coreboot.org/pipermail/coreboot/2017-June/084538.html

On 09/15/2017 12:40 PM, Fabian wrote:
> Hi everyone,
>
> I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB.

The H8SCM has serial ports that are routed via the winbond BMC chip 
slash pseudo super I/O, I too have been unable to get output on it.
> One more question to the AMD experts: There are two motherboard models "H8SCM" and "H8SCM (Fam10)". Whats the difference?

AFAIK The first is AGESA the second was a port to the native init code, 
however that port no longer works (and I believe neither of them work 
these days)

I believe the simplest way to get started on getting coreboot to work on 
this board is to get a PCI-e serial card that has a serial controller 
matching the model that coreboot supports (I believe the oxford 
OXPCIe952, see the device ID's under generic drivers in menuconfig)
It is what I am going to do when I get the time.

[Kyösti Mälkki]

On Fri, Sep 15, 2017 at 7:40 PM, Fabian  wrote:
> Hi everyone,
>
> I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB. So I want to give SPI console a try. It seems to be a very new feature introduced here [1].

Do you have a tested usbdebug setup with some other coreboot mainboard?

Not sure if that works either, but do you have 7-seg POST card for PCI slot?

Currently, for H8SCM, console on usb would start in ramstage.. which
is way too late to be useful for you. It makes things otherwise
unstable, but you can have USBDEBUG_IN_ROMSTAGE=y by modifying
drivers/usb/Kconfig:

config USBDEBUG_IN_ROMSTAGE
      depends on EARLY_CBMEM_INIT    << remove
> When I compile coreboot it fails with this warning:
> warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CONSOLE_SPI_FLASH) selects BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY which has unmet direct dependencies (SPI_FLASH && BOOT_DEVICE_SPI_FLASH_RW_NOMMAP)
>
> As written in [1] it's only tested for Skylake. How much effort is necessary to port it to my board? Are there more Information about SPI console? Or is there an other way to get log from my board?

SPI master controller (flash write) support has not been implemented
for SB700 southbridge. It's probably a matter of including
cimx/sb800/spi.c in your build (with some PCI ID changes) and adding
"select SPI_FLASH". Then again, once you enable FMAP for SPI console
use, you probably break AGESA build elsewhere.
There are some assumptions left (for AGESA and binaryPI) that CBFS
would cover the complete SPI flash part.

Kyösti