FIDVID question

[Dan Lykowski]

I have narrowed the resetting of my board to:

Referring to real_main in cache_as_ram.c for dbm690t and pistachio.
msr=rdmsr(0xc0010042); ( Reading the FIDVID_STAUS register )

According to the docs, trying to read this register on a processor that doesn't support FID/VID changes will cause a GP#. 
I was under the assumption that all mobile 0Fh processors had this capability.
Would calling enable_fid_change() before the rdmsr call enable the MSR? ( I am skeptical because the code is working for other processors. )
Would it be appropriate to add a check around the FIDVID sections?

struct cpuid_result cpuid1;
cpuid1 = cpuid(0x8000007);
if( (cpuid1.edx & 0x06) == 0x06 ) {
}

S1G1 Sempron 2100+ 9W 1Ghz

Thanks,
Dan Lykowski

Hi,

if you check your CPUID, does it support FIDVID?

If yes, then there is another problem. Perhaps you are hit by
some errata which says first is needed not HT reset (LDTSTOP) but PCI reset.
I don't have a code at my hand right now, but is HT reset stuff done
_before_ the fidvid?

Thanks,
Rudolf

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[Marc Jones]

On Thu, Jan 8, 2009 at 1:45 AM,   wrote:
> Hi,
>
> if you check your CPUID, does it support FIDVID?
>
> If yes, then there is another problem. Perhaps you are hit by
> some errata which says first is needed not HT reset (LDTSTOP) but PCI reset.
> I don't have a code at my hand right now, but is HT reset stuff done
> _before_ the fidvid?

I think that all the revf/g processors support fidvid even if it can't
be changed. The S1G1 socket means revf and above and checking for
support really isn't needed. I think it is safe for a platform to make
some assumptions like that.

Have you narrowed the reset to the fidvid code?  After fidvid setup
there should be a ht reset as Rudolf noted. You can skip fidvid setup
for now. It just means that the processor will run at min frequency.

Marc