I have narrowed the resetting of my board to: Referring to real_main in cache_as_ram.c for dbm690t and pistachio. msr=rdmsr(0xc0010042); ( Reading the FIDVID_STAUS register ) According to the docs, trying to read this register on a processor that doesn't support FID/VID changes will cause a GP#. I was under the assumption that all mobile 0Fh processors had this capability. Would calling enable_fid_change() before the rdmsr call enable the MSR? ( I am skeptical because the code is working for other processors. ) Would it be appropriate to add a check around the FIDVID sections? struct cpuid_result cpuid1; cpuid1 = cpuid(0x8000007); if( (cpuid1.edx & 0x06) == 0x06 ) { } S1G1 Sempron 2100+ 9W 1Ghz Thanks, Dan Lykowski