On Pn, 2011-08-19 at 21:55 +0530, Abhinav Hardikar wrote:
Hi,
I did as you said and the POST code referred to ./arch/x86/lib/c_start.S:85:
And no I don't get any serial messages.
Thanx, Abhinav
Please when replying use "Reply to all" or manually make sure that coreboot@coreboot.org is included in cc: or to: fields.
Could you please add what other post codes are you getting before the last one?
Sorry abt that. Damn those codes are displayed so fast. I had to use a camera to capture them.
I get the following codes:
10,11,40,24,25,55,66,9b
24 is ./cpu/intel/model_6ex/cache_as_ram.inc:254: 25 is ./cpu/intel/model_106cx/cache_as_ram.inc:244:
Thanx Abhinav
10,11,40,24,25,55,66,9b
24 is ./cpu/intel/model_6ex/cache_as_ram.inc:254: 25 is ./cpu/intel/model_106cx/cache_as_ram.inc:244:
could you add more post codes somewhere around this: ./boot/hardwaremain.c:105: cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
Ok. I added the post code but it isn't displayed on the card. And I haven't added any payload as the chip is only 128K and needs 47KB more to accommodate SeaBIOS.
Abhinav
________________________________ From: Tadas Slotkus <devtadas@gmail.com> To: Abhinav Hardikar <ahardyx@yahoo.in> Cc: "coreboot@coreboot.org" <coreboot@coreboot.org> Sent: Friday, 19 August 2011 10:59 PM Subject: Re: [coreboot] POST code error "EE"
> 10,11,40,24,25,55,66,9b > > > 24 is ./cpu/intel/model_6ex/cache_as_ram.inc:254: > 25 is ./cpu/intel/model_106cx/cache_as_ram.inc:244:
could you add more post codes somewhere around this: ./boot/hardwaremain.c:105: cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
Is your serial cable really working?
I recommend you to remove unneeded microcode updates. Check what is your cpu model/cpuid and remove unneded stuff like I did: for example I have modified these files: ./cpu/intel/slot_1/Makefile.inc // leave only your models ./cpu/intel/model_65x/model_65x_init.c //comment microcode includes
this should fit everything to ~80 kB
Ok....
I think the file ./boot/hardwaremain.c:105: wasn't compiled earlier. I commented the post code in the file as you said and it showed 26 which is hardwaremain.c
________________________________
Ok
I did as you said. my CPU id was 68x and that was not added in the Slot-1 Makefile. Your method of removing all other CPUs created a lot of space. So I added SeaBIOS. Coreboot started working. It didn't give any error. But the keyboard is not working so are the serial ports. The Null modem cable is working. I checked it with HyperTerminal and minicom.
BTW its midnight here. I'll do the rest tomorrow. Thanx for your help :)
Abhinav
________________________________ From: Tadas Slotkus <devtadas@gmail.com> To: Abhinav Hardikar <ahardyx@yahoo.in> Cc: "coreboot@coreboot.org" <coreboot@coreboot.org> Sent: Friday, 19 August 2011 11:26 PM Subject: Re: [coreboot] POST code error "EE"
Is your serial cable really working?
I recommend you to remove unneeded microcode updates. Check what is your cpu model/cpuid and remove unneded stuff like I did: for example I have modified these files: ./cpu/intel/slot_1/Makefile.inc // leave only your models ./cpu/intel/model_65x/model_65x_init.c //comment microcode includes
this should fit everything to ~80 kB
Coreboot started working. It didn't give any error.
That's great to hear it! One more board will be supported :)
But the keyboard is not working so are the serial ports. The Null modem cable is working. I checked it with HyperTerminal and minicom.
You could try extracting pirq table from vendor BIOS using this tool from coreboot: util/getpir
What is the board that you based on your experiments? :)
BTW its midnight here. I'll do the rest tomorrow. Thanx for your help :)
No problem :)
But the keyboard is not working so are the serial ports.
You could look if the right superio is selected in the config.
And yes I forgot to add I used the following coreboot images of:
Abit Abit BE6-II V2.0 ASUS P2B-F ASUS P2B-LS ASUS P3B-F AZZA PT-6IBD MSI MS-6119
All of them worked well but keyb didn't.
Also you could comment that line where you get post code in ./arch/x86/lib/c_start.S:85: so you could see the last post code you want.