Hi all, I'm wondering if it's possible to place code into cache-emulated RAM, I tested on an intel T2300, after CAR setup, I can read/write to the mapped region, however code execution seems not working. Postcode reveals that the CPU seems to be spinning on the very first instruction in the 'RAM' region.
Anyone could give some hints? thanks.
On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan jackiepan93@gmail.com wrote:
Hi all, I'm wondering if it's possible to place code into cache-emulated RAM, I tested on an intel T2300, after CAR setup, I can read/write to the mapped region, however code execution seems not working. Postcode reveals that the CPU seems to be spinning on the very first instruction in the 'RAM' region. Anyone could give some hints? thanks.
It is possible and it works. What you might do is dump the contents of the CAR once you have copied to it and see what is there.
ron
On Fri, Sep 5, 2008 at 12:46 AM, ron minnich rminnich@gmail.com wrote:
On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan jackiepan93@gmail.com wrote:
Hi all, I'm wondering if it's possible to place code into cache-emulated RAM, I tested on an intel T2300, after CAR setup, I can read/write to the mapped region, however code execution seems not working. Postcode reveals that the CPU seems to be spinning on the very first instruction in the 'RAM' region. Anyone could give some hints? thanks.
It is possible and it works. What you might do is dump the contents of the CAR once you have copied to it and see what is there.
in v2, there is one option for Opteron rev F, after enable it, DDR2 mem
training code is copied to core0 cache of other nodes, it will train the mem when core0 of node0 is doing hardware_main(),,,,
YH
On 05.09.2008 09:46, ron minnich wrote:
On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan jackiepan93@gmail.com wrote:
I'm wondering if it's possible to place code into cache-emulated RAM, I tested on an intel T2300, after CAR setup, I can read/write to the mapped region, however code execution seems not working. Postcode reveals that the CPU seems to be spinning on the very first instruction in the 'RAM' region. Anyone could give some hints? thanks.
It is possible and it works. What you might do is dump the contents of the CAR once you have copied to it and see what is there.
Yes and no. At least the new AMD Family 10h processors can't use CAR for data storage and code storage at the same time. In theory, you could fill the CAR area in data storage mode, then switch over to code storage. Not tested, though, and NOT mentioned as viable in the BKDG (BIOS and Kernel Developer's Guide).
Intel CPUs might have similar restrictions.
Regards, Carl-Daniel
Core 2 Duo can do cache for ram and code... But it works well enough to just set an mtrr to make rom cacheable during car and that also works for older intel CPUs
On 05.09.2008, at 11:44, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net
wrote:
On 05.09.2008 09:46, ron minnich wrote:
On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan jackiepan93@gmail.com wrote:
I'm wondering if it's possible to place code into cache-emulated RAM, I tested on an intel T2300, after CAR setup, I can read/write to the mapped region, however code execution seems not working. Postcode reveals that the CPU seems to be spinning on the very first instruction in the 'RAM' region. Anyone could give some hints? thanks.
It is possible and it works. What you might do is dump the contents of the CAR once you have copied to it and see what is there.
Yes and no. At least the new AMD Family 10h processors can't use CAR for data storage and code storage at the same time. In theory, you could fill the CAR area in data storage mode, then switch over to code storage. Not tested, though, and NOT mentioned as viable in the BKDG (BIOS and Kernel Developer's Guide).
Intel CPUs might have similar restrictions.
Regards, Carl-Daniel
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On 05.09.2008 12:54, Stefan Reinauer wrote:
On 05.09.2008 09:45, Jackie Pan wrote:
if it's possible to place code into cache-emulated RAM
Core 2 Duo can do cache for ram and code... But it works well enough to just set an mtrr to make rom cacheable during car and that also works for older intel CPUs
We're talking about different things. Jackie was talking about executing code stored inside the pseudo-RAM CAR area. I was talking about that as well. Stefan wrote about using cache for code outside the CAR area.
Regards, Carl-Daniel
Carl-Daniel Hailfinger wrote:
On 05.09.2008 12:54, Stefan Reinauer wrote:
On 05.09.2008 09:45, Jackie Pan wrote:
if it's possible to place code into cache-emulated RAM
Core 2 Duo can do cache for ram and code... But it works well enough to just set an mtrr to make rom cacheable during car and that also works for older intel CPUs
We're talking about different things. Jackie was talking about executing code stored inside the pseudo-RAM CAR area. I was talking about that as well. Stefan wrote about using cache for code outside the CAR area.
No, not at all different things. As I said, the Core 2 Duo can execute code stored in CAR.
2008/9/5 Stefan Reinauer stepan@coresystems.de
Carl-Daniel Hailfinger wrote:
On 05.09.2008 12:54, Stefan Reinauer wrote:
On 05.09.2008 09:45, Jackie Pan wrote:
if it's possible to place code into cache-emulated RAM
Core 2 Duo can do cache for ram and code... But it works well enough to just set an mtrr to make rom cacheable during car and that also works for older intel CPUs
We're talking about different things. Jackie was talking about executing code stored inside the pseudo-RAM CAR area. I was talking about that as well. Stefan wrote about using cache for code outside the CAR area.
No, not at all different things. As I said, the Core 2 Duo can execute code stored in CAR.
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Hi Stefan,
I'm very curious about how you achieve this. As Intel's separate L1 data cache and instruction cache,after checking the prog. manual I come to the conclusion that the i-cache can only be filled by instruction fetching process(or am i wrong?), when I copy code into the CAR region(i.e., not by caching of the XIP region using MTRR), the data I supplied goes directly into the d-cache, at the same time the corresponding line in the i-cache(if any) gets invalidated immediately, or more exactly for the CAR case, there's no such line in the i-cache at all because there's not been any instruction fetching targeting at the CAR region before. Thus it seems impossible to synchronize the i-cache and d-cache without a RAM as backup.
let me guess, are you implying storing to another core's cache while using MESI for the purpose of synchronizing?
Jackie Pan wrote:
I'm very curious about how you achieve this. As Intel's separate L1 data cache and instruction cache, after checking the prog. manual I come to the conclusion that the i-cache can only be filled by instruction fetching process(or am i wrong?), when I copy code into the CAR region(i.e., not by caching of the XIP region using MTRR), the data I supplied goes directly into the d-cache, at the same time the corresponding line in the i-cache(if any) gets invalidated immediately, or more exactly for the CAR case, there's no such line in the i-cache at all because there's not been any instruction fetching targeting at the CAR region before. Thus it seems impossible to synchronize the i-cache and d-cache without a RAM as backup.
let me guess, are you implying storing to another core's cache while using MESI for the purpose of synchronizing?
I don't know much about MESI except it exists. But for CAR as we do it on Intel CPUs it is essential that we keep all AP cores in Wait for SIPI state to get them out of the way. They're only re-activated when RAM is working, at which point we're using ram based semaphores.
Stefan
On Fri, Sep 5, 2008 at 2:44 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Yes and no. At least the new AMD Family 10h processors can't use CAR for data storage and code storage at the same time. In theory, you could fill the CAR area in data storage mode, then switch over to code storage. Not tested, though, and NOT mentioned as viable in the BKDG (BIOS and Kernel Developer's Guide).
hmm, this will mean a redesign in v3 if true.
We count on using CAR for code (initram)
ron
On 05.09.2008 16:50, ron minnich wrote:
On Fri, Sep 5, 2008 at 2:44 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Yes and no. At least the new AMD Family 10h processors can't use CAR for data storage and code storage at the same time. In theory, you could fill the CAR area in data storage mode, then switch over to code storage. Not tested, though, and NOT mentioned as viable in the BKDG (BIOS and Kernel Developer's Guide).
hmm, this will mean a redesign in v3 if true.
Not really. v3 does not try to load any code into the CAR area.
We count on using CAR for code (initram)
initram is not loaded into the CAR area, it is XIP in the ROM.
Let me rephrase: On Fam10h, it is not possible to _store_ code and read/write data in a given CAR area. Depending on CAR granularity, you can designate each part of the CAR area for a different purpose. Example: CAR as code storage (readonly) from 0xc8000-0xc8fff, CAR as data storage (read/write) from 0xc9000-0xcffff.
Regards, Carl-Daniel
On Fri, Sep 5, 2008 at 8:01 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 05.09.2008 16:50, ron minnich wrote:
hmm, this will mean a redesign in v3 if true.
Not really. v3 does not try to load any code into the CAR area.
you're right. Ron, drink more coffee. Sorry, was up very late.
ron
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Carl-Daniel Hailfinger -
Jackie Pan -
ron minnich -
Stefan Reinauer -
yhlu