Hello,
Sorry to come back on this old thread but I would greatly appreciate if anyone could update the info discussed in it. Is the SDRAM CAS latency parameter the only issue with EPIA 800 ? Does the newest version of LB adapt itself to different SDRAMs ?
Finally, Al, you were talking about :
"keeping track of what it takes to get this going on EPIA, so I can post it for others in the future, this will be good to know."
Could you kindly share your tracks with the EPIA 800 ? Thanks
Hacen
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I'm going to be trying epia 800 and sc520 in january after vacation. THe 8601 is a problem chipset, and most attempts to make it more flexible generally result in the chipset locknig up in other scenarios. My original, crude code was pretty reliable, the most reliable code in fact. But it would still be nice to have LB more flexible with this chipset.
ron
Hello Ron,
Following your previous email, I am coming to the news regarding the EPIA 800. Anything new ? Or perhaps is it too soon ...
hacen
ron minnich wrote:
I'm going to be trying epia 800 and sc520 in january after vacation. THe 8601 is a problem chipset, and most attempts to make it more flexible generally result in the chipset locknig up in other scenarios. My original, crude code was pretty reliable, the most reliable code in fact. But it would still be nice to have LB more flexible with this chipset.
ron
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Hacen Aissaoui wrote:
Hello Ron,
Following your previous email, I am coming to the news regarding the EPIA 800. Anything new ? Or perhaps is it too soon ...
I am finishing a firefighting exercise and then hope to get back to this problem.
ron