[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Ed Swierk]

The early init code of several Intel southbridge chipsets calls
pci_locate_device() to locate the SMBus controller and LPC bridge
devices on the PCI bus. Since these devices are always located at a
fixed PCI bus:device:function, the code can be simplified by
hardcoding the devices.

Signed-off-by: Ed Swierk

[PATCH] Hardcode PCI devices in Intel southbridge early init code

Quoting Ed Swierk :
> The early init code of several Intel southbridge chipsets calls
> pci_locate_device() to locate the SMBus controller and LPC bridge
> devices on the PCI bus. Since these devices are always located at a
> fixed PCI bus:device:function, the code can be simplified by
> hardcoding the devices.
>
> Signed-off-by: Ed Swierk

Looks good, but I don't think we need to add any patches to the  
i82801ca, i82801db, i82801dbm, or i82801er. The southbridge code for  
these should not be used, and should be
dropped. Everyone should be using the i82801xx code for all ICH's. I  
propose we drop that
code now that the i82801xx is stable, so cool people like Ed do not  
waste their time on
it :-)

Thanks - Joe

[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Corey Osgood]

On Mon, Mar 31, 2008 at 1:16 PM,  wrote:
> Quoting Ed Swierk :
> > The early init code of several Intel southbridge chipsets calls
> > pci_locate_device() to locate the SMBus controller and LPC bridge
> > devices on the PCI bus. Since these devices are always located at a
> > fixed PCI bus:device:function, the code can be simplified by
> > hardcoding the devices.
> >
> > Signed-off-by: Ed Swierk
>
> Looks good, but I don't think we need to add any patches to the
> i82801ca, i82801db, i82801dbm, or i82801er. The southbridge code for
> these should not be used, and should be
> dropped. Everyone should be using the i82801xx code for all ICH's. I
> propose we drop that
> code now that the i82801xx is stable, so cool people like Ed do not
> waste their time on
> it :-)
>
> Thanks - Joe

As the guy who put together the i82801xx, I'd have to NAK that. If we had
more boards to test it on (especially the ones already in the tree, like the
intel dev boards and tyan board), then I'd say go for it, but not until we
know it works in place of the current chips. When I put together the
i82801xx, I tried to "steal" the best code from all of them, and put
together something that would be as generic and full-featured as possible.
In the process, I got rid of some system-specific bits, especially from the
i82801er, that may have been required for the systems that used them. I
would say it's probably safe to drop the i82801dbm, since it's not used by
any ports and you're using that chip with the rm4100.

-Corey

[PATCH] Hardcode PCI devices in Intel southbridge early init code

Quoting Corey Osgood :
> On Mon, Mar 31, 2008 at 1:16 PM,  wrote:
> > Quoting Ed Swierk :
> > > The early init code of several Intel southbridge chipsets calls
> > > pci_locate_device() to locate the SMBus controller and LPC bridge
> > > devices on the PCI bus. Since these devices are always located at a
> > > fixed PCI bus:device:function, the code can be simplified by
> > > hardcoding the devices.
> > >
> > > Signed-off-by: Ed Swierk
> >
> > Looks good, but I don't think we need to add any patches to the
> > i82801ca, i82801db, i82801dbm, or i82801er. The southbridge code for
> > these should not be used, and should be
> > dropped. Everyone should be using the i82801xx code for all ICH's. I
> > propose we drop that
> > code now that the i82801xx is stable, so cool people like Ed do not
> > waste their time on
> > it :-)
> >
> > Thanks - Joe
>
> As the guy who put together the i82801xx, I'd have to NAK that. If we had
> more boards to test it on (especially the ones already in the tree, like the
> intel dev boards and tyan board), then I'd say go for it, but not until we
> know it works in place of the current chips. When I put together the
> i82801xx, I tried to "steal" the best code from all of them, and put
> together something that would be as generic and full-featured as possible.
> In the process, I got rid of some system-specific bits, especially from the
> i82801er, that may have been required for the systems that used them. I
> would say it's probably safe to drop the i82801dbm, since it's not used by
> any ports and you're using that chip with the rm4100.

Ack that. The RM4100 has a i82801DB ICH4 and I am using the i82801xx  
code. The original i82801DB code never worked right, so can we at  
least drop that one?

Thanks - Joe

[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Uwe Hermann]

On Mon, Mar 31, 2008 at 04:04:59PM -0400, [e-mail] wrote:
> Ack that. The RM4100 has a i82801DB ICH4 and I am using the i82801xx  
> code. The original i82801DB code never worked right, so can we at  
> least drop that one?

We should only drop code where all boards in svn have been migrated to
i82801xx (and tested!) to be on the safe side. I.e. if there's an
ICH* southbridge which is no longer used by any board, drop it (but only
in that case). If this means we keep the old code around for the time being,
that's fine.

But of course we should

- Make all _new_ boards work with i82801xx only (not the other ones)

- Only port the i82801xx to v3 (not the other ones)

Uwe.

[PATCH] Hardcode PCI devices in Intel southbridge early init code

Quoting Uwe Hermann :
> On Mon, Mar 31, 2008 at 04:04:59PM -0400, [e-mail] wrote:
> > Ack that. The RM4100 has a i82801DB ICH4 and I am using the i82801xx
> > code. The original i82801DB code never worked right, so can we at
> > least drop that one?
>
> We should only drop code where all boards in svn have been migrated to
> i82801xx (and tested!) to be on the safe side. I.e. if there's an
> ICH* southbridge which is no longer used by any board, drop it (but only
> in that case). If this means we keep the old code around for the time being,
> that's fine.
>
> But of course we should
>
> Make all _new_ boards work with i82801xx only (not the other ones)
>
> Only port the i82801xx to v3 (not the other ones)

Like I said the i82801DB has never work and no ther boards use it.......
Ok, so how do we drop i82801DB via svn? Do we need ACK, Sign-off, etc?

Thanks - Joe

[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Corey Osgood]

On Mon, Mar 31, 2008 at 4:32 PM,  wrote:
> Quoting Uwe Hermann :
> > On Mon, Mar 31, 2008 at 04:04:59PM -0400, [e-mail]:
> > > Ack that. The RM4100 has a i82801DB ICH4 and I am using the i82801xx
> > > code. The original i82801DB code never worked right, so can we at
> > > least drop that one?
> >
> > We should only drop code where all boards in svn have been migrated to
> > i82801xx (and tested!) to be on the safe side. I.e. if there's an
> > ICH* southbridge which is no longer used by any board, drop it (but only
> > in that case). If this means we keep the old code around for the time
>
> being,
> > that's fine.
> >
> > But of course we should
> >
> > Make all _new_ boards work with i82801xx only (not the other ones)
> >
> > Only port the i82801xx to v3 (not the other ones)
>
> Like I said the i82801DB has never work and no ther boards use it.......
> Ok, so how do we drop i82801DB via svn? Do we need ACK, Sign-off, etc?
>
> Thanks - Joe

Use "svn rm", and yes, you'd need an ack that I'd be happy to provide. Make
sure you abuild test it, just to make sure that there's no board we've
forgotten about that's using it. If there is, I'm 90% sure it's the one with
the i855 northbridge, and that's never worked either, so probably all of it
could be dropped.

-Corey

[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Corey Osgood]

On Mon, Mar 31, 2008 at 4:37 PM, Corey Osgood 
wrote:
> On Mon, Mar 31, 2008 at 4:32 PM,  wrote:
> > Quoting Uwe Hermann :
> > > On Mon, Mar 31, 2008 at 04:04:59PM -0400, [e-mail]:
> > > > Ack that. The RM4100 has a i82801DB ICH4 and I am using the i82801xx
> > > > code. The original i82801DB code never worked right, so can we at
> > > > least drop that one?
> > >
> > > We should only drop code where all boards in svn have been migrated to
> > > i82801xx (and tested!) to be on the safe side. I.e. if there's an
> > > ICH* southbridge which is no longer used by any board, drop it (but
> >
> > only
> > > in that case). If this means we keep the old code around for the time
> >
> > being,
> > > that's fine.
> > >
> > > But of course we should
> > >
> > > Make all _new_ boards work with i82801xx only (not the other ones)
> > >
> > > Only port the i82801xx to v3 (not the other ones)
> >
> > Like I said the i82801DB has never work and no ther boards use it.......
> > Ok, so how do we drop i82801DB via svn? Do we need ACK, Sign-off, etc?
> >
> > Thanks - Joe
>
> Use "svn rm", and yes, you'd need an ack that I'd be happy to provide.
> Make sure you abuild test it, just to make sure that there's no board we've
> forgotten about that's using it. If there is, I'm 90% sure it's the one with
> the i855 northbridge, and that's never worked either, so probably all of it
> could be dropped.
>
> -Corey

Yep, it's the digitallogic/adl855pc. I think it was Ron that said the 855
never worked, but that was a long time ago, and I can't be sure.  Perhaps we
should just leave it kicking around, and focus on not letting this happen to
v3.

-Corey

[PATCH] Hardcode PCI devices in Intel southbridge early init code

Quoting Corey Osgood :
> On Mon, Mar 31, 2008 at 4:37 PM, Corey Osgood 
> wrote:
> > On Mon, Mar 31, 2008 at 4:32 PM,  wrote:
> > > Quoting Uwe Hermann :
> > > > On Mon, Mar 31, 2008 at 04:04:59PM -0400,
> >
> > [e-mail]:
> > > > > Ack that. The RM4100 has a i82801DB ICH4 and I am using the i82801xx
> > > > > code. The original i82801DB code never worked right, so can we at
> > > > > least drop that one?
> > > >
> > > > We should only drop code where all boards in svn have been migrated to
> > > > i82801xx (and tested!) to be on the safe side. I.e. if there's an
> > > > ICH* southbridge which is no longer used by any board, drop it (but
> > >
> > > only
> > > > in that case). If this means we keep the old code around for the time
> > >
> > > being,
> > > > that's fine.
> > > >
> > > > But of course we should
> > > >
> > > > Make all _new_ boards work with i82801xx only (not the other ones)
> > > >
> > > > Only port the i82801xx to v3 (not the other ones)
> > >
> > > Like I said the i82801DB has never work and no ther boards use it.......
> > > Ok, so how do we drop i82801DB via svn? Do we need ACK, Sign-off, etc?
> > >
> > > Thanks - Joe
> >
> > Use "svn rm", and yes, you'd need an ack that I'd be happy to provide.
> > Make sure you abuild test it, just to make sure that there's no board we've
> > forgotten about that's using it. If there is, I'm 90% sure it's the one with
> > the i855 northbridge, and that's never worked either, so probably all of it
> > could be dropped.
> >
> > -Corey
>
> Yep, it's the digitallogic/adl855pc. I think it was Ron that said the 855
> never worked, but that was a long time ago, and I can't be sure.  Perhaps we
> should just leave it kicking around, and focus on not letting this happen to
> v3.

Nope. The digitallogic/adl855pc uses the i82801DBM (ICH-4M). I am  
talking about the i82801DB (ICH4). Two different chipsets. There are  
no boards that use the i82801DB (ICH4). The code does NOT work.

Removal of i82801DB (ICH4)
Signed-off-by: Joseph Smith

Thanks - Joe

[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Corey Osgood]

On Mon, Mar 31, 2008 at 5:00 PM,  wrote:
> Quoting Corey Osgood :
> > On Mon, Mar 31, 2008 at 4:37 PM, Corey Osgood 
> > wrote:
> > > On Mon, Mar 31, 2008 at 4:32 PM,  wrote:
> > > > Quoting Uwe Hermann :
> > > > > On Mon, Mar 31, 2008 at 04:04:59PM -0400,
> > >
> > > [e-mail]:
> > > > > > Ack that. The RM4100 has a i82801DB ICH4 and I am using the
>
> i82801xx
> > > > > > code. The original i82801DB code never worked right, so can we at
> > > > > > least drop that one?
> > > > >
> > > > > We should only drop code where all boards in svn have been migrated
>
> to
> > > > > i82801xx (and tested!) to be on the safe side. I.e. if there's an
> > > > > ICH* southbridge which is no longer used by any board, drop it (but
> > > >
> > > > only
> > > > > in that case). If this means we keep the old code around for the
>
> time
> > > > being,
> > > > > that's fine.
> > > > >
> > > > > But of course we should
> > > > > Make all _new_ boards work with i82801xx only (not the other
>
> ones)
> > > > > Only port the i82801xx to v3 (not the other ones)
> > > >
> > > > Like I said the i82801DB has never work and no ther boards use
>
> it.......
> > > > Ok, so how do we drop i82801DB via svn? Do we need ACK, Sign-off,
>
> etc?
> > > > Thanks - Joe
> > >
> > > Use "svn rm", and yes, you'd need an ack that I'd be happy to provide.
> > > Make sure you abuild test it, just to make sure that there's no board
>
> we've
> > > forgotten about that's using it. If there is, I'm 90% sure it's the one
>
> with
> > > the i855 northbridge, and that's never worked either, so probably all
>
> of it
> > > could be dropped.
> > >
> > > -Corey
> >
> > Yep, it's the digitallogic/adl855pc. I think it was Ron that said the
>
> 855
> > never worked, but that was a long time ago, and I can't be sure.
>
> Perhaps we
> > should just leave it kicking around, and focus on not letting this
>
> happen to
> > v3.
>
> Nope. The digitallogic/adl855pc uses the i82801DBM (ICH-4M). I am
> talking about the i82801DB (ICH4). Two different chipsets. There are
> no boards that use the i82801DB (ICH4). The code does NOT work.
>
> Removal of i82801DB (ICH4)
> Signed-off-by: Joseph Smith
>
> Thanks - Joe

The patch is missing, but when it gets here its
Acked-by: Corey Osgood

[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Stefan Reinauer]

Corey Osgood wrote:
> Yep, it's the digitallogic/adl855pc. I think it was Ron that said the 
> 855 never worked, but that was a long time ago, and I can't be sure.  
> Perhaps we should just leave it kicking around, and focus on not 
> letting this happen to v3.

I can confirm that code does nothing good. I have a mostly ready 855 
port sitting somewhere that I wrote from flash. I will look into this 
when/if I get the machine again I was originally writing it for.

[PATCH] Hardcode PCI devices in Intel southbridge early init code

Quoting Stefan Reinauer :
> Corey Osgood wrote:
> > Yep, it's the digitallogic/adl855pc. I think it was Ron that said   
> > the 855 never worked, but that was a long time ago, and I can't be   
> > sure.  Perhaps we should just leave it kicking around, and focus on  
> >  not letting this happen to v3.
>
> I can confirm that code does nothing good. I have a mostly ready 855
> port sitting somewhere that I wrote from flash. I will look into this
> when/if I get the machine again I was originally writing it for.

No worries, I will be working on a board in the near future that uses  
the i82801dbm (ICH4-M) and I will verify it works with the i82801xx  
code. If everything works ok, I will submit a patch to switch over the  
digitallogic/adl855pc and remove the i82801dbm code.

Thanks - Joe

[PATCH] Hardcode PCI devices in Intel southbridge early init code

[Corey Osgood]

On Mon, Mar 31, 2008 at 11:50 AM, Ed Swierk  wrote:
> The early init code of several Intel southbridge chipsets calls
> pci_locate_device() to locate the SMBus controller and LPC bridge
> devices on the PCI bus. Since these devices are always located at a
> fixed PCI bus:device:function, the code can be simplified by
> hardcoding the devices.
>
> Signed-off-by: Ed Swierk

Acked-by: Corey Osgood

Index: coreboot-v2-3189/src/southbridge/intel/esb6300/esb6300_early_smbus.c
> ===================================================================
> --- coreboot-v2-3189.orig
> /src/southbridge/intel/esb6300/esb6300_early_smbus.c
> +++ coreboot-v2-3189/src/southbridge/intel/esb6300/esb6300_early_smbus.c
> @@ -4,12 +4,8 @@
>
> static void enable_smbus(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(0x8086, 0x25a4), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("SMBUS controller not found\r\n");
> }
> uint8_t enable;
> device_t dev = PCI_DEV(0, 0x1f, 3);
> print_spew("SMBus controller enabled\r\n");
>    pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
>    pci_write_config8(dev, 0x40, 1);
>
> @@ -19,11 +15,6 @@ static void enable_smbus(void)
>  /* Disable interrupt generation */
>  outb(0, SMBUS_IO_BASE + SMBHSTCTL);
> dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("ISA bridge not found\r\n");
> }
>
> }
>
> static int smbus_read_byte(unsigned device, unsigned address)
> Index: coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_lpc.c
> ===================================================================
> --- coreboot-v2-3189.orig/src/southbridge/intel/i3100/i3100_early_lpc.c
> +++ coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_lpc.c
> @@ -20,12 +20,7 @@
>
> static void i3100_enable_superio(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
>                   PCI_DEVICE_ID_INTEL_3100_LPC), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("LPC bridge not found\r\n");
> }
>
> device_t dev = PCI_DEV(0, 0x1f, 0);
>
> /* Enable decoding of I/O locations for SuperIO devices */
> pci_write_config16(dev, 0x82, 0x340f);
>
> @@ -33,12 +28,7 @@ static void i3100_enable_superio(void)
>
> static void i3100_halt_tco_timer(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
>                   PCI_DEVICE_ID_INTEL_3100_LPC), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("LPC bridge not found\r\n");
> }
>
> device_t dev = PCI_DEV(0, 0x1f, 0);
>
> /* Temporarily enable the ACPI I/O range at 0x4000 */
> pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
> Index: coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_smbus.c
>
> --- coreboot-v2-3189.orig/src/southbridge/intel/i3100/i3100_early_smbus.c
> +++ coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_smbus.c
> @@ -24,12 +24,8 @@
>
> static void enable_smbus(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
>                   PCI_DEVICE_ID_INTEL_3100_SMB), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("SMBus controller not found\r\n");
> }
> device_t dev = PCI_DEV(0, 0x1f, 3);
> print_spew("SMBus controller enabled\r\n");
>    pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
>    pci_write_config8(dev, 0x40, 1);
>
> Index:
> coreboot-v2-3189/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
> ===================================================================
> --- coreboot-v2-3189.orig
> /src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
> +++ coreboot-v2-3189/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
> @@ -3,12 +3,8 @@
>
> static void enable_smbus(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
>
> PCI_DEVICE_ID_INTEL_82801CA_SMB), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("SMBUS controller not found\r\n");
> }
> device_t dev = PCI_DEV(0, 0x1f, 3);
> print_debug("SMBus controller enabled\r\n");
>    /* set smbus iobase */
>    pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE |
>
> PCI_BASE_ADDRESS_SPACE_IO);
> Index:
> coreboot-v2-3189/src/southbridge/intel/i82801db/i82801db_early_smbus.c
> ===================================================================
> --- coreboot-v2-3189.orig
> /src/southbridge/intel/i82801db/i82801db_early_smbus.c
> +++ coreboot-v2-3189/src/southbridge/intel/i82801db/i82801db_early_smbus.c
> @@ -22,13 +22,10 @@
>
> static void enable_smbus(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("SMBUS controller not found\r\n");
> }
> device_t dev = PCI_DEV(0, 0x1f, 3);
> print_spew("SMBus controller enabled\r\n");
> pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
>    /* Set smbus enable */
>    pci_write_config8(dev, 0x40, 1);
>
> @@ -36,19 +33,12 @@ static void enable_smbus(void)
>      pci_write_config8(dev, 0x4, 1);
>      /* SMBALERT_DIS */
>      pci_write_config8(dev, 0x11, 4);
>
> /* Disable interrupt generation */
>    outb(0, SMBUS_IO_BASE + SMBHSTCTL);
>
> /* clear any lingering errors, so the transaction will run */
>    outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
>
> -#if 0    // It's unlikely that half the southbridge suddenly vanishes?
> dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("ISA bridge not found\r\n");
> }
>
> -#endif
>  }
>
> static int smbus_read_byte(unsigned device, unsigned address)
> Index:
> coreboot-v2-3189/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
> ===================================================================
> --- coreboot-v2-3189.orig
> /src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
> +++
> coreboot-v2-3189/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
> @@ -21,12 +21,8 @@
>
> static void enable_smbus(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(0x8086, 0x24c3), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("SMBUS controller not found\r\n");
> }
> device_t dev = PCI_DEV(0, 0x1f, 3);
> print_debug("SMBus controller enabled\r\n");
>    /* set smbus iobase */
>    pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
>
> Index:
> coreboot-v2-3189/src/southbridge/intel/i82801er/i82801er_early_smbus.c
> ===================================================================
> --- coreboot-v2-3189.orig
> /src/southbridge/intel/i82801er/i82801er_early_smbus.c
> +++ coreboot-v2-3189/src/southbridge/intel/i82801er/i82801er_early_smbus.c
> @@ -4,13 +4,10 @@
>
> static void enable_smbus(void)
>  {
> device_t dev;
> dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("SMBUS controller not found\r\n");
> }
> device_t dev = PCI_DEV(0, 0x1f, 3);
> print_spew("SMBus controller enabled\r\n");
> pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
>    /* Set smbus enable */
>    pci_write_config8(dev, 0x40, 1);
>
> @@ -18,19 +15,12 @@ static void enable_smbus(void)
>      pci_write_config8(dev, 0x4, 1);
>      /* SMBALERT_DIS */
>      pci_write_config8(dev, 0x11, 4);
>
> /* Disable interrupt generation */
>    outb(0, SMBUS_IO_BASE + SMBHSTCTL);
>
> /* clear any lingering errors, so the transaction will run */
>    outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
>
> -#if 0    // It's unlikely that half the southbridge suddenly vanishes?
> dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
> if (dev == PCI_DEV_INVALID) {
>    die("ISA bridge not found\r\n");
> }
>
> -#endif
>  }
>
> static int smbus_read_byte(unsigned device, unsigned address)