[LinuxBIOS] [PATCH] AMD Barcelona(family 10) support 2 of 4 - coreboot

13 Dec 2007

AMD 8111 southbridge adjustments for Barcelona.
Marc
-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones@amd.com
http://www.amd.com/embeddedprocessors

Additional early AMD8111 southbridge support for Barcelona platforms.
Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.


Signed-off-by: Marc Jones marc.jones@amd.com
Reviewed-by: Jordan Crouse jordan.crouse@amd.com

Index: LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_smbus.c
===================================================================

--- LinuxBIOSv2.orig/src/southbridge/amd/amd8111/amd8111_early_smbus.c	2007-12-12 14:29:48.000000000 -0700
+++ LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_smbus.c	2007-12-12 14:30:02.000000000 -0700
@@ -5,17 +5,25 @@
 static void enable_smbus(void)
 {
    device_t dev;
+	uint8_t enable;
+
    dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
    if (dev == PCI_DEV_INVALID) {
    	die("SMBUS controller not found\r\n");
    }
-	uint8_t enable;
-	print_spew("SMBus controller enabled\r\n");
+
    pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
    enable = pci_read_config8(dev, 0x41);
    pci_write_config8(dev, 0x41, enable | (1 << 7));
+
+	/* check that we can see the smbus controller I/O. */
+	if (inw(SMBUS_IO_BASE)==0xFF){
+		die("SMBUS controller I/O not found\n");
+	}
+
    /* clear any lingering errors, so the transaction will run */
    outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
+	print_spew("SMBus controller enabled\r\n");
 }

 static int smbus_recv_byte(unsigned device)
Index: LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/amd8111/amd8111_early_ctrl.c	2007-12-12 14:29:48.000000000 -0700
+++ LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c	2007-12-12 14:30:02.000000000 -0700
@@ -14,25 +14,33 @@

 }

-static void hard_reset(void)
+static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
 {
-        device_t dev;
-        unsigned bus;
+	device_t dev;
+	uint8_t byte;

-        /* Find the device.
-         * There can only be one 8111 on a hypertransport chain/bus.
-         */
-        bus = get_sbbusn(get_sblk());
-        dev = pci_locate_device_on_bus(
-                PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI),
-                bus);
+	dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
+	/* enable cf9 */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= (1<<6) | (1<<5);
+	pci_write_config8(dev, 0x41, byte);
+}

-        set_bios_reset();
+static void enable_cf9(void)
+{
+	unsigned sblk = get_sblk();
+	unsigned sbbusn = get_sbbusn(sblk);
+	unsigned sbdn = get_sbdn(sbbusn);
+
+	enable_cf9_x(sbbusn, sbdn);
+}

-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
+static void hard_reset(void)
+{
+        set_bios_reset();
         /* reset */
-        outb(0x0e, 0x0cf9);
+        enable_cf9();
+        outb(0x0e, 0x0cf9); // make sure cf9 is enabled
 }

 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)

    