Author: myles Date: 2008-11-18 17:59:09 +0100 (Tue, 18 Nov 2008) New Revision: 1042
Modified: coreboot-v3/northbridge/amd/k8/pci.c Log: This patch fixes white space in northbridge/amd/pci with the help of indent.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Myles Watson mylesgw@gmail.com
Modified: coreboot-v3/northbridge/amd/k8/pci.c =================================================================== --- coreboot-v3/northbridge/amd/k8/pci.c 2008-11-17 22:24:11 UTC (rev 1041) +++ coreboot-v3/northbridge/amd/k8/pci.c 2008-11-18 16:59:09 UTC (rev 1042) @@ -47,163 +47,166 @@ #include <lapic.h>
#define FX_DEVS 8 -extern struct device * __f0_dev[FX_DEVS]; +extern struct device *__f0_dev[FX_DEVS]; extern void get_fx_devs(void); u32 f1_read_config32(unsigned int reg); void f1_write_config32(unsigned int reg, u32 value); -unsigned int amdk8_nodeid(struct device * dev); +unsigned int amdk8_nodeid(struct device *dev);
-static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) +static unsigned int amdk8_scan_chain(struct device *dev, unsigned nodeid, + unsigned link, unsigned sblink, + unsigned int max, unsigned offset_unitid) {
- u32 link_type; - int i; - u32 busses, config_busses; - unsigned free_reg, config_reg; - unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain - unsigned max_bus; - unsigned min_bus; - unsigned max_devfn; - printk(BIOS_SPEW, "amdk8_scan_chain link %x\n",link); - dev->link[link].cap = 0x80 + (link *0x20); - do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); - } while(link_type & ConnectionPending); - if (!(link_type & LinkConnected)) { - return max; + u32 link_type; + int i; + u32 busses, config_busses; + unsigned free_reg, config_reg; + unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain + unsigned max_bus; + unsigned min_bus; + unsigned max_devfn; + printk(BIOS_SPEW, "amdk8_scan_chain link %x\n", link); + dev->link[link].cap = 0x80 + (link * 0x20); + do { + link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + } while (link_type & ConnectionPending); + if (!(link_type & LinkConnected)) { + return max; + } + printk(BIOS_DEBUG, "amdk8_scan_chain: link %d is connected\n", link); + do { + link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + } while (!(link_type & InitComplete)); + if (!(link_type & NonCoherent)) { + return max; + } + /* See if there is an available configuration space mapping + * register in function 1. + */ + free_reg = 0; + for (config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { + u32 config; + config = f1_read_config32(config_reg); + if (!free_reg && ((config & 3) == 0)) { + free_reg = config_reg; + continue; } - printk(BIOS_DEBUG, "amdk8_scan_chain: link %d is connected\n", link); - do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); - } while(!(link_type & InitComplete)); - if (!(link_type & NonCoherent)) { - return max; + if (((config & 3) == 3) && + (((config >> 4) & 7) == nodeid) && + (((config >> 8) & 3) == link)) { + break; } - /* See if there is an available configuration space mapping - * register in function 1. - */ - free_reg = 0; - for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { - u32 config; - config = f1_read_config32(config_reg); - if (!free_reg && ((config & 3) == 0)) { - free_reg = config_reg; - continue; - } - if (((config & 3) == 3) && - (((config >> 4) & 7) == nodeid) && - (((config >> 8) & 3) == link)) { - break; - } - } - if (free_reg && (config_reg > 0xec)) { - config_reg = free_reg; - } - /* If we can't find an available configuration space mapping - * register skip this bus - */ - if (config_reg > 0xec) { - return max; - } + } + if (free_reg && (config_reg > 0xec)) { + config_reg = free_reg; + } + /* If we can't find an available configuration space mapping + * register skip this bus + */ + if (config_reg > 0xec) { + return max; + }
- /* Set up the primary, secondary and subordinate bus numbers. - * We have no idea how many busses are behind this bridge yet, - * so we set the subordinate bus number to 0xff for the moment. - */ + /* Set up the primary, secondary and subordinate bus numbers. + * We have no idea how many busses are behind this bridge yet, + * so we set the subordinate bus number to 0xff for the moment. + */ #if SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if((nodeid == 0) && (sblink==link)) { // actually max is 0 here - min_bus = max; - } + // first chain will on bus 0 + if ((nodeid == 0) && (sblink == link)) { // actually max is 0 here + min_bus = max; + } #if SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; + // second chain will be on 0x40, third 0x80, forth 0xc0 + else { + min_bus = ((max >> 6) + 1) * 0x40; + } + max = min_bus; #else - //other ... - else { - min_bus = ++max; - } + //other ... + else { + min_bus = ++max; + } #endif #else - min_bus = ++max; + min_bus = ++max; #endif - max_bus = 0xff; + max_bus = 0xff;
- dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; + dev->link[link].secondary = min_bus; + dev->link[link].subordinate = max_bus;
- /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, dev->link[link].cap + 0x14); - config_busses = f1_read_config32(config_reg); + /* Read the existing primary/secondary/subordinate bus + * number configuration. + */ + busses = pci_read_config32(dev, dev->link[link].cap + 0x14); + config_busses = f1_read_config32(config_reg);
- /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xff000000; - busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(dev->link[link].secondary) << 8) | - ((unsigned int)(dev->link[link].subordinate) << 16)); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagates by the bridge if it is + * not correctly configured + */ + busses &= 0xff000000; + busses |= (((unsigned int)(dev->bus->secondary) << 0) | + ((unsigned int)(dev->link[link].secondary) << 8) | + ((unsigned int)(dev->link[link].subordinate) << 16)); + pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
- config_busses &= 0x000fc88; - config_busses |= - (3 << 0) | /* rw enable, no device compare */ - (( nodeid & 7) << 4) | - (( link & 3 ) << 8) | - ((dev->link[link].secondary) << 16) | - ((dev->link[link].subordinate) << 24); - f1_write_config32(config_reg, config_busses); + config_busses &= 0x000fc88; + config_busses |= (3 << 0) | /* rw enable, no device compare */ + ((nodeid & 7) << 4) | + ((link & 3) << 8) | + ((dev->link[link].secondary) << 16) | + ((dev->link[link].subordinate) << 24); + f1_write_config32(config_reg, config_busses);
- /* Now we can scan all of the subordinate busses i.e. the - * chain on the hypertranport link - */ - for(i=0;i<4;i++) { - ht_unitid_base[i] = 0x20; - } + /* Now we can scan all of the subordinate busses i.e. the + * chain on the hypertranport link + */ + for (i = 0; i < 4; i++) { + ht_unitid_base[i] = 0x20; + }
- if (min_bus == 0) - max_devfn = (0x17<<3) | 7; - else - max_devfn = (0x1f<<3) | 7; + if (min_bus == 0) + max_devfn = (0x17 << 3) | 7; + else + max_devfn = (0x1f << 3) | 7;
- max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); + max = + hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, + ht_unitid_base, offset_unitid);
- /* We know the number of busses behind this bridge. Set the - * subordinate bus number to it's real value - */ - dev->link[link].subordinate = max; - busses = (busses & 0xff00ffff) | - ((unsigned int) (dev->link[link].subordinate) << 16); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + /* We know the number of busses behind this bridge. Set the + * subordinate bus number to it's real value + */ + dev->link[link].subordinate = max; + busses = (busses & 0xff00ffff) | + ((unsigned int)(dev->link[link].subordinate) << 16); + pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
- config_busses = (config_busses & 0x00ffffff) | - (dev->link[link].subordinate << 24); - f1_write_config32(config_reg, config_busses); + config_busses = (config_busses & 0x00ffffff) | + (dev->link[link].subordinate << 24); + f1_write_config32(config_reg, config_busses);
- { - // config config_reg, and ht_unitid_base to update hcdn_reg; - int index; - unsigned temp = 0; - index = (config_reg-0xe0) >> 2; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } + { + // config config_reg, and ht_unitid_base to update hcdn_reg; + int index; + unsigned temp = 0; + index = (config_reg - 0xe0) >> 2; + for (i = 0; i < 4; i++) { + temp |= (ht_unitid_base[i] & 0xff) << (i * 8); + }
- sysconf.hcdn_reg[index] = temp; + sysconf.hcdn_reg[index] = temp;
- } + }
printk(BIOS_SPEW, "amdk8_scan_chain done\n"); return max; }
-static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max) +static unsigned int amdk8_scan_chains(struct device *dev, unsigned int max) { unsigned nodeid; unsigned link; @@ -213,31 +216,35 @@
printk(BIOS_DEBUG, "amdk8_scan_chains\n");
- if(nodeid==0) { - sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + if (nodeid == 0) { + sblink = (pci_read_config32(dev, 0x64) >> 8) & 3; #if SB_HT_CHAIN_ON_BUS0 > 0 - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; - #endif +#endif // do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2, // but put 8151 on link0 - max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); + max = + amdk8_scan_chain(dev, nodeid, sblink, sblink, max, + offset_unitid); #endif }
- for(link = 0; link < dev->links; link++) { + for (link = 0; link < dev->links; link++) { #if SB_HT_CHAIN_ON_BUS0 > 0 - if( (nodeid == 0) && (sblink == link) ) continue; //already done + if ((nodeid == 0) && (sblink == link)) + continue; //already done #endif offset_unitid = 0; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if((nodeid == 0) && (sblink == link)) - #endif - offset_unitid = 1; - #endif +#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + if ((nodeid == 0) && (sblink == link)) +#endif + offset_unitid = 1; +#endif
- max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + max = amdk8_scan_chain(dev, nodeid, link, sblink, max, + offset_unitid); }
return max; @@ -253,32 +260,32 @@ * __f0 is initialized once in amdk8_read_resources */ static int reg_useable(unsigned reg, - struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) + struct device *goal_dev, unsigned goal_nodeid, + unsigned goal_link) { struct resource *res; - unsigned nodeid, link=0; + unsigned nodeid, link = 0; int result; res = NULL;
/* Look for the resource that matches this register. */ - for(nodeid = 0; !res && (nodeid < CONFIG_MAX_PHYSICAL_CPUS); nodeid++) { - struct device * dev; + for (nodeid = 0; !res && (nodeid < CONFIG_MAX_PHYSICAL_CPUS); nodeid++) { + struct device *dev; dev = __f0_dev[nodeid]; - if (! dev) + if (!dev) continue; - for(link = 0; !res && (link < 3); link++) { + for (link = 0; !res && (link < 3); link++) { res = probe_resource(dev, 0x100 + (reg | link)); } } - + /* If no allocated resource was found, it is free - return 2 */ result = 2; if (res) { result = 0; /* If the resource is allocated to the link and node already */ - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) { result = 1; } } @@ -286,20 +293,20 @@ return result; }
-static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdk8_find_iopair(struct device *dev, unsigned nodeid, + unsigned link) { struct resource *resource; unsigned free_reg, reg; resource = NULL; free_reg = 0; - for(reg = 0xc0; reg <= 0xd8; reg += 0x8) { + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { int result; result = reg_useable(reg, dev, nodeid, link); if (result == 1) { /* I have been allocated this one */ break; - } - else if (result > 1) { + } else if (result > 1) { /* I have a free register pair */ free_reg = reg; } @@ -313,20 +320,20 @@ return resource; }
-static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) +static struct resource *amdk8_find_mempair(struct device *dev, unsigned nodeid, + unsigned link) { struct resource *resource; unsigned free_reg, reg; resource = NULL; free_reg = 0; - for(reg = 0x80; reg <= 0xb8; reg += 0x8) { + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { int result; result = reg_useable(reg, dev, nodeid, link); if (result == 1) { /* I have been allocated this one */ break; - } - else if (result > 1) { + } else if (result > 1) { /* I have a free register pair */ free_reg = reg; } @@ -340,70 +347,73 @@ return resource; }
-static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device *dev, unsigned nodeid, + unsigned link) { struct resource *resource;
/* Initialize the io space constraints on the current bus */ - resource = amdk8_find_iopair(dev, nodeid, link); + resource = amdk8_find_iopair(dev, nodeid, link); if (resource) { - resource->base = 0; - resource->size = 0; + resource->base = 0; + resource->size = 0; resource->align = log2c(HT_IO_HOST_ALIGN); - resource->gran = log2c(HT_IO_HOST_ALIGN); + resource->gran = log2c(HT_IO_HOST_ALIGN); resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); + IORESOURCE_IO, IORESOURCE_IO); }
/* Initialize the prefetchable memory constraints on the current bus */ resource = amdk8_find_mempair(dev, nodeid, link); if (resource) { - resource->base = 0; - resource->size = 0; + resource->base = 0; + resource->size = 0; resource->align = log2c(HT_MEM_HOST_ALIGN); - resource->gran = log2c(HT_MEM_HOST_ALIGN); + resource->gran = log2c(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH); }
/* Initialize the memory constraints on the current bus */ resource = amdk8_find_mempair(dev, nodeid, link); if (resource) { - resource->base = 0; - resource->size = 0; + resource->base = 0; + resource->size = 0; resource->align = log2c(HT_MEM_HOST_ALIGN); - resource->gran = log2c(HT_MEM_HOST_ALIGN); + resource->gran = log2c(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM; compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM); } }
-static void amdk8_read_resources(struct device * dev) +static void amdk8_read_resources(struct device *dev) { printk(BIOS_DEBUG, "amdk8_read_resources\n"); unsigned nodeid, link; nodeid = amdk8_nodeid(dev);
- get_fx_devs(); /* Make sure __f0 is initialized*/ + get_fx_devs(); /* Make sure __f0 is initialized */
- for(link = 0; link < dev->links; link++) { + for (link = 0; link < dev->links; link++) { if (dev->link[link].children) { - printk(BIOS_DEBUG, "amdk8_read_resources link %d\n", link); + printk(BIOS_DEBUG, "amdk8_read_resources link %d\n", + link); amdk8_link_read_bases(dev, nodeid, link); } } printk(BIOS_DEBUG, "amdk8_read_resources done\n"); }
-static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device *dev, struct resource *resource, + unsigned nodeid) { resource_t rbase, rend; unsigned reg, link; @@ -431,29 +441,30 @@ rbase = resource->base;
/* Get the limit (rounded up) */ - rend = resource_end(resource); + rend = resource_end(resource);
/* Get the register and link */ - reg = resource->index & 0xfc; + reg = resource->index & 0xfc; link = resource->index & 3;
if (resource->flags & IORESOURCE_IO) { u32 base, limit; compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); - base = f1_read_config32(reg); + IORESOURCE_IO, IORESOURCE_IO); + base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x4); - base &= 0xfe000fcc; - base |= rbase & 0x01fff000; - base |= 3; + base &= 0xfe000fcc; + base |= rbase & 0x01fff000; + base |= 3; limit &= 0xfe000fc8; limit |= rend & 0x01fff000; limit |= (link & 3) << 4; limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n", - __func__, dev_path(dev), link); + printk(BIOS_SPEW, + "%s, enabling legacy VGA IO forwarding for %s link %x\n", + __func__, dev_path(dev), link); base |= PCI_IO_BASE_VGA_EN; } if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { @@ -462,17 +473,18 @@
f1_write_config32(reg + 0x4, limit); f1_write_config32(reg, base); - } - else if (resource->flags & IORESOURCE_MEM) { + } else if (resource->flags & IORESOURCE_MEM) { u32 base, limit; compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)); - base = f1_read_config32(reg); + IORESOURCE_MEM | IORESOURCE_PREFETCH, + resource-> + flags & (IORESOURCE_MEM | + IORESOURCE_PREFETCH)); + base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x4); - base &= 0x000000f0; - base |= (rbase >> 8) & 0xffffff00; - base |= 3; + base &= 0x000000f0; + base |= (rbase >> 8) & 0xffffff00; + base |= 3; limit &= 0x00000048; limit |= (rend >> 8) & 0xffffff00; limit |= (link & 3) << 4; @@ -481,8 +493,7 @@ f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %d link %d>", - nodeid, link); + sprintf(buf, " <node %d link %d>", nodeid, link); report_resource_stored(dev, resource, buf); }
@@ -492,10 +503,10 @@ * but it is too diffcult to deal with the resource allocation magic. */ #ifdef CONFIG_MULTIPLE_VGA_INIT -extern struct device * vga_pri; // the primary vga device, defined in device.c +extern struct device *vga_pri; // the primary vga device, defined in device.c #endif
-static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid) { struct resource *resource; unsigned link; @@ -507,14 +518,19 @@ for (link = 0; link < dev->links; link++) { if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #ifdef CONFIG_MULTIPLE_VGA_INIT - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, - dev->link[link].secondary,dev->link[link].subordinate); + printk(BIOS_DEBUG, + "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", + vga_pri->bus->secondary, + dev->link[link].secondary, + dev->link[link].subordinate); /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= dev->link[link].secondary ) && - (vga_pri->bus->secondary <= dev->link[link].subordinate ) - ) + if ((vga_pri->bus->secondary >= + dev->link[link].secondary) + && (vga_pri->bus->secondary <= + dev->link[link].subordinate) + ) #endif - break; + break; } }
@@ -522,24 +538,26 @@ if (link == dev->links) return;
- printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", + dev_path(dev), nodeid, link);
/* allocate a temp resrouce for legacy VGA buffer */ resource = amdk8_find_mempair(dev, nodeid, link); - if(!resource){ - printk(BIOS_DEBUG, "VGA: Can not find free mmio reg for legacy VGA buffer\n"); + if (!resource) { + printk(BIOS_DEBUG, + "VGA: Can not find free mmio reg for legacy VGA buffer\n"); return; } resource->base = 0xa0000; resource->size = 0x20000;
/* write the resource to the hardware */ - reg = resource->index & 0xfc; - base = f1_read_config32(reg); + reg = resource->index & 0xfc; + base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x4); - base &= 0x000000f0; - base |= (resource->base >> 8) & 0xffffff00; - base |= 3; + base &= 0x000000f0; + base |= (resource->base >> 8) & 0xffffff00; + base |= 3; limit &= 0x00000048; limit |= (resource_end(resource) >> 8) & 0xffffff00; limit |= (resource->index & 3) << 4; @@ -551,7 +569,7 @@ resource->flags = 0; }
-static void amdk8_set_resources(struct device * dev) +static void amdk8_set_resources(struct device *dev) { unsigned nodeid, link; int i; @@ -563,11 +581,11 @@ amdk8_create_vga_resource(dev, nodeid);
/* Set each resource we have found */ - for(i = 0; i < dev->resources; i++) { + for (i = 0; i < dev->resources; i++) { amdk8_set_resource(dev, &dev->resource[i], nodeid); }
- for(link = 0; link < dev->links; link++) { + for (link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; if (bus->children) { @@ -576,7 +594,7 @@ } }
-static void amdk8_enable_resources(struct device * dev) +static void amdk8_enable_resources(struct device *dev) { printk(BIOS_DEBUG, "amdk8_enable_resources\n"); pci_dev_enable_resources(dev); @@ -596,8 +614,8 @@
struct device_operations k8_ops = { .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x1100}}}, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = 0x1100}}}, .constructor = default_device_constructor, .reset_bus = pci_bus_reset, .phase3_scan = amdk8_scan_chains, @@ -606,5 +624,5 @@ .phase5_enable_resources = amdk8_enable_resources, .phase6_init = mcf0_control_init, .ops_pci = &pci_dev_ops_pci, - .ops_pci_bus = &pci_cf8_conf1, + .ops_pci_bus = &pci_cf8_conf1, };
-
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