Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h

2 Oct 2008

Hi Uwe,
thanks for cleaning up the codeing style.
However, it seems that indent also did some readability damage. Could
you perhaps fix up these places?
Review follows.
Regards,
Carl-Daniel
On 02.10.2008 20:19, svn@coreboot.org wrote:
...
Author: uwe
Date: 2008-10-02 20:19:17 +0200 (Thu, 02 Oct 2008)
New Revision: 3631
Log:
CK804 coding-style fixed based on an 'indent' run (trivial).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h

--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h	2008-10-02 18:19:17 UTC (rev 3631)
@@ -1,8 +1,7 @@
 #ifndef CK804_CHIP_H
 #define CK804_CHIP_H
-struct southbridge_nvidia_ck804_config
-{
+struct southbridge_nvidia_ck804_config {
   unsigned int usb1_hc_reset : 1;
   unsigned int ide0_enable : 1;
   unsigned int ide1_enable : 1;
@@ -16,4 +15,4 @@
 struct chip_operations;
 extern struct chip_operations southbridge_nvidia_ck804_ops;
-#endif /* CK804_CHIP_H */
+#endif
Was the change above intentional?
...
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -4,9 +4,7 @@
  */
#include <console/console.h>



#include <arch/io.h>



#include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -15,178 +13,167 @@
static uint32_t final_reg;
-static device_t find_lpc_dev( device_t dev,  unsigned devfn) 
+static device_t find_lpc_dev(device_t dev, unsigned devfn)
 {

device_t lpc_dev;

   lpc_dev = dev_find_slot(dev->bus->secondary, devfn);




lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
if (!lpc_dev)
return lpc_dev;





   if ( !lpc_dev ) return lpc_dev;




if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA)
|| ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC)


&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO)


&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)))


{
uint32_t id;


id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);


if ((id != (PCI_VENDOR_ID_NVIDIA |


      (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16)))


    && (id != (PCI_VENDOR_ID_NVIDIA |


	 (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16)))


    && (id != (PCI_VENDOR_ID_NVIDIA |


	 (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))))


{


	lpc_dev = 0;


}


}


   if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (


(lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) &&


           (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) &&


           (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)) ) {


           	uint32_t id;


                   id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);


                   if ( (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) &&


                   	(id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) &&


		(id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))


		) {


                          lpc_dev = 0;


   		}


   }


return lpc_dev;

}
void ck804_enable(device_t dev)
 {
   device_t lpc_dev;

unsigned index = 0;
unsigned index2 = 0;


unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;

Confusing, see also below.
...
uint32_t reg_old, reg;
   uint8_t byte;

unsigned deviceid;

unsigned vendorid;

   struct southbridge_nvidia_ck804_config *conf;


   conf = dev->chip_info;




struct southbridge_nvidia_ck804_config *conf;
conf = dev->chip_info;


unsigned devfn;

if(dev->device==0x0000) {


if (dev->device == 0x0000) {
vendorid = pci_read_config32(dev, PCI_VENDOR_ID);


deviceid = (vendorid>>16) & 0xffff;



-//		vendorid &= 0xffff;

deviceid = (vendorid >> 16) & 0xffff;


/* vendorid &= 0xffff; */

} else {

-//		vendorid = dev->vendor;

/* vendorid = dev->vendor; */

deviceid = dev->device;
}
devfn = (dev->path.u.pci.devfn) & ~7;



switch(deviceid) {
case PCI_DEVICE_ID_NVIDIA_CK804_SM:


	index = 16;


	break;


case PCI_DEVICE_ID_NVIDIA_CK804_USB:


	devfn -= (1<<3);


	index = 8;


	break;


           case PCI_DEVICE_ID_NVIDIA_CK804_USB2:


                   devfn -= (1<<3);


                   index = 20;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_NIC:


                   devfn -= (9<<3);


                   index = 10;


	dev->rom_address = conf->nic_rom_address;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:


                   devfn -= (9<<3);


                   index = 10;


                   dev->rom_address = conf->nic_rom_address;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_ACI:


                   devfn -= (3<<3);


                   index = 12;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_MCI:


                   devfn -= (3<<3);


                   index = 13;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_IDE:


                   devfn -= (5<<3);


                   index = 14;


	dev->rom_address = conf->raid_rom_address;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:


                   devfn -= (6<<3);


                   index = 22;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:


                   devfn -= (7<<3);


                   index = 18;


                   break;


           case PCI_DEVICE_ID_NVIDIA_CK804_PCI:


                   devfn -= (8<<3);


                   index = 15;


                   break;


case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:


	devfn -= (0xa<<3);


	index2 = 19;


	break;


default:


	index = 0;




switch (deviceid) {
case PCI_DEVICE_ID_NVIDIA_CK804_SM:
index = 16;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_USB:
devfn -= (1 << 3);


index = 8;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
devfn -= (1 << 3);


index = 20;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
devfn -= (9 << 3);


index = 10;


dev->rom_address = conf->nic_rom_address;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
devfn -= (9 << 3);


index = 10;


dev->rom_address = conf->nic_rom_address;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
devfn -= (3 << 3);


index = 12;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
devfn -= (3 << 3);


index = 13;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
devfn -= (5 << 3);


index = 14;


dev->rom_address = conf->raid_rom_address;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
devfn -= (6 << 3);


index = 22;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
devfn -= (7 << 3);


index = 18;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
devfn -= (8 << 3);


index = 15;


break;


case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
devfn -= (0xa << 3);


index2 = 19;


break;


default:
index = 0;

}


if(index2!=0) {


if (index2 != 0) {
int i;


for(i=0;i<4;i++) {


	lpc_dev = find_lpc_dev(dev, devfn - (i<<3));


	if(!lpc_dev) continue;




for (i = 0; i < 4; i++) {


	lpc_dev = find_lpc_dev(dev, devfn - (i << 3));


	if (!lpc_dev)


		continue;
index2 -= i;
break;

}


if ( lpc_dev ) {


               reg_old = reg =  pci_read_config32(lpc_dev, 0xe4);



	if (!dev->enabled) { 


		reg |= (1<<index2);


	}



           	if (reg != reg_old) {


                   	pci_write_config32(lpc_dev, 0xe4, reg);


           	}




if (lpc_dev) {


	reg_old = reg = pci_read_config32(lpc_dev, 0xe4);


	if (!dev->enabled)


		reg |= (1 << index2);


	if (reg != reg_old)


		pci_write_config32(lpc_dev, 0xe4, reg);

}
index2 = 0;
return;
}



lpc_dev = find_lpc_dev(dev, devfn);


if (!lpc_dev)
return;





if ( !lpc_dev )	return;

   if ( index == 0) {





if (index == 0) {
final_reg = pci_read_config32(lpc_dev, 0xe8);


final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<10)|(1<<12)|(1<<13)|(1<<14)|(1<<22)|(1<<18)|(1<<15));


pci_write_config32(lpc_dev, 0xe8, final_reg); 




final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10)


	| (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22)


	| (1 << 18) | (1 << 15));


pci_write_config32(lpc_dev, 0xe8, final_reg);





           reg_old = reg = pci_read_config32(lpc_dev, 0xe4);


           reg |= (1<<20);


           if (reg != reg_old) {


                   pci_write_config32(lpc_dev, 0xe4, reg);


           }




reg_old = reg = pci_read_config32(lpc_dev, 0xe4);


reg |= (1 << 20);


if (reg != reg_old)


	pci_write_config32(lpc_dev, 0xe4, reg);





           byte = pci_read_config8(lpc_dev, 0x74);


           byte |= ((1<<1)); 


           pci_write_config8(dev, 0x74, byte);




byte = pci_read_config8(lpc_dev, 0x74);


byte |= ((1 << 1));


pci_write_config8(dev, 0x74, byte);





           byte = pci_read_config8(lpc_dev, 0xdd);


           byte |= ((1<<0)|(1<<3)); 


           pci_write_config8(dev, 0xdd, byte);




byte = pci_read_config8(lpc_dev, 0xdd);


byte |= ((1 << 0) | (1 << 3));


pci_write_config8(dev, 0xdd, byte);


return;

}



   }




if (!dev->enabled)
final_reg |= (1 << index);





if (!dev->enabled) {
           final_reg |= (1 << index);


   }



if(index == 10 ) {


if (index == 10) {
reg_old = pci_read_config32(lpc_dev, 0xe8);


   	if (final_reg != reg_old) {


           	pci_write_config32(lpc_dev, 0xe8, final_reg);


   	}





if (final_reg != reg_old)


	pci_write_config32(lpc_dev, 0xe8, final_reg);

}




}
struct chip_operations southbridge_nvidia_ck804_ops = {
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h	2008-10-02 18:19:17 UTC (rev 3631)
@@ -5,4 +5,4 @@
void ck804_enable(device_t dev);
-#endif /* CK804_H */
+#endif
Comment removal.
...
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@

Copyright 2004 Tyan Computer
by yhlu@tyan.com

*/



#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -11,19 +12,19 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {

   pci_write_config32(dev, 0x40,


           ((device & 0xffff) << 16) | (vendor & 0xffff));




pci_write_config32(dev, 0x40,
	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}
static struct pci_operations lops_pci = {

   .set_subsystem = lpci_set_subsystem,




.set_subsystem = lpci_set_subsystem,

};
-static struct device_operations ac97audio_ops  = {
+static struct device_operations ac97audio_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

This actually kills readable indentation.
...
.init             = 0,
   .scan_bus         = 0,
   .ops_pci          = &lops_pci,
@@ -35,12 +36,11 @@
   .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI,
 };



-static struct device_operations ac97modem_ops  = {
+static struct device_operations ac97modem_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Same here.
...
.init             = 0,
   .scan_bus         = 0,
   .ops_pci          = &lops_pci,
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@

Copyright 2004 Tyan Computer
by yhlu@tyan.com

*/



static int set_ht_link_ck804(uint8_t ht_c_num)
 {
   unsigned vendorid = 0x10de;
@@ -9,10 +10,10 @@
   return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
-static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
+static void setup_ss_table(unsigned index, unsigned where, unsigned control,

	   const unsigned int *register_values, int max)



{
   int i;

unsigned val;
val = inl(control);


@@ -21,7 +22,7 @@
outl(0, index);

for(i = 0; i < max; i++) {


for (i = 0; i < max; i++) {
unsigned long reg;
reg = register_values[i];
outl(reg, where);

@@ -29,67 +30,61 @@
   val = inl(control);
   val |= 1;
   outl(val, control);



}
#define ANACTRL_IO_BASE 0x7000
 #define ANACTRL_REG_POS 0x68



#define SYSCTRL_IO_BASE 0x6000
 #define SYSCTRL_REG_POS 0x64
/*

16 1 1 2 :0
8 8 2 2 :1


8 8 4   :2


8 4 4 4 :3


16 4     :4



16 1 1 2 :0



8 8 2 2 :1





8 8 4   :2





8 4 4 4 :3





16 4     :4



*/
#ifndef CK804_PCI_E_X

#define CK804_PCI_E_X 4

+#define CK804_PCI_E_X 4
 #endif
#if CK804_NUM > 1

#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000)
#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000)

#ifndef CK804B_BUSN
#define CK804B_BUSN 0x80


#endif

#ifndef CK804B_PCI_E_X
#define CK804B_PCI_E_X 4


#endif

+#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
+#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
+#ifndef CK804B_BUSN
+#define CK804B_BUSN 0x80
 #endif
+#ifndef CK804B_PCI_E_X
+#define CK804B_PCI_E_X 4
+#endif
+#endif
#ifndef CK804_USE_NIC

#define CK804_USE_NIC 0

+#define CK804_USE_NIC 0
 #endif
#ifndef CK804_USE_ACI

#define CK804_USE_ACI 0

+#define CK804_USE_ACI 0
 #endif
#define CK804_CHIP_REV 3
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE

#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE

+#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
 #else

#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE

+#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
 #endif
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1

#define CK804B_DEVN_BASE 1

+#define CK804B_DEVN_BASE 1
 #else

#define CK804B_DEVN_BASE CK804_DEVN_BASE

+#define CK804B_DEVN_BASE CK804_DEVN_BASE
 #endif



static void ck804_early_set_port(void)
 {

static const unsigned int ctrl_devport_conf[] = {
  PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,

#if CK804_NUM > 1
@@ -103,12 +98,10 @@
   };
setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));



}
static void ck804_early_clear_port(void)
 {

static const unsigned int ctrl_devport_conf_clear[] = {
  PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,

#if CK804_NUM > 1
@@ -122,84 +115,70 @@
   };
setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));



}
static void ck804_early_setup(void)
 {

static const unsigned int ctrl_conf[] = {


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,



RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,



#if CK804_NUM > 1

RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,

#endif

RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,



RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,



#if CK804_NUM > 1

RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,

#endif

RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,


#if CK804_NUM > 1

RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,

#endif

RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,


#if CK804_NUM > 1

RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,

#endif

RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,




#if CK804_NUM > 1

RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,

#endif

RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,

@@ -208,139 +187,125 @@
   RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,

RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),

#if CK804_NUM > 1

RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,


#endif

RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,

#if CK804_NUM > 1
   RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 #endif

// Activate master port on primary SATA controller
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000,


/* Activate master port on primary SATA controller. */
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,

#if  CK804_NUM > 1

RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,



RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,

#endif


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),

#if CK804_NUM > 1

RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),

#endif

RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,

#if CK804_NUM > 1

RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,

#endif

RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),


RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),

#if CK804_NUM > 1

RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),

#endif



RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),

#if CK804_USE_NIC == 1

RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),


RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),

#endif
#if CK804_USE_ACI == 1

RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),

#endif
#if CK804_NUM > 1

RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),

#endif



#if CK804_NUM > 1

#if CK804_USE_NIC == 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,


RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),


RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),


RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),


#endif

+#if CK804_USE_NIC == 1

RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),

#endif
+#endif




#ifdef CK804_MB_SETUP
   CK804_MB_SETUP
 #endif

};


setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf));

setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);

setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);

setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);



setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);

#if CK804_NUM > 1

setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64);
setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64);
setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64);


setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);

#endif
#if 0
   dump_io_resources(ANACTRL_IO_BASE);
   dump_io_resources(SYSCTRL_IO_BASE);
 #endif



}
static int ck804_early_setup_x(void)
@@ -369,4 +334,3 @@
   outb(0x06, 0x0cf9);
 #endif
 }



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -11,365 +11,339 @@
   return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
-static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
+static void setup_ss_table(unsigned index, unsigned where, unsigned control,

	   const unsigned int *register_values, int max)



{
   int i;

unsigned val;


val = inl(control);
 val &= 0xfffffffe;
 outl(val, control);
outl(0, index);



for(i = 0; i < max; i++) {


for (i = 0; i < max; i++) {
unsigned long reg;


reg = register_values[i];
  outl(reg, where);
 }


val = inl(control);
 val |= 1;
 outl(val, control);




}
#define ANACTRL_IO_BASE 0x3000
 #define ANACTRL_REG_POS 0x68



#define SYSCTRL_IO_BASE 0x2000
 #define SYSCTRL_REG_POS 0x64
/*

16 1 1 2 :0
8 8 2 2 :1


8 8 4   :2


8 4 4 4 :3


16 4     :4



16 1 1 2 :0



8 8 2 2 :1





8 8 4   :2





8 4 4 4 :3





16 4     :4



*/
#ifndef CK804_PCI_E_X

#define CK804_PCI_E_X 4

+#define CK804_PCI_E_X 4
 #endif

/* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */
#define CK804B_ANACTRL_IO_BASE 0x3000
#define CK804B_SYSCTRL_IO_BASE 0x2000

+/*


We will use the offset in setup_resource_map_x_offset and



setup_resource_map_offset.


*/

+#define CK804B_ANACTRL_IO_BASE 0x3000
+#define CK804B_SYSCTRL_IO_BASE 0x2000

#ifdef CK804B_BUSN
#undef CK804B_BUSN


#endif
#define CK804B_BUSN 0x0

+#ifdef CK804B_BUSN
+#undef CK804B_BUSN
+#endif
+#define CK804B_BUSN 0x0

#ifndef CK804B_PCI_E_X
#define CK804B_PCI_E_X 4


#endif

+#ifndef CK804B_PCI_E_X
+#define CK804B_PCI_E_X 4
+#endif
#ifndef CK804_USE_NIC

#define CK804_USE_NIC 0

+#define CK804_USE_NIC 0
 #endif
#ifndef CK804_USE_ACI

#define CK804_USE_ACI 0

+#define CK804_USE_ACI 0
 #endif
#define CK804_CHIP_REV 3
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE

#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE

+#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
 #else

#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE

+#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
 #endif
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1

#define CK804B_DEVN_BASE 1

+#define CK804B_DEVN_BASE 1
 #else

#define CK804B_DEVN_BASE CK804_DEVN_BASE

+#define CK804B_DEVN_BASE CK804_DEVN_BASE
 #endif
-static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
+static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,

		 unsigned *io_base)



{

static const unsigned int ctrl_devport_conf[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,


PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,




PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,


PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,

};
static const unsigned int ctrl_devport_conf_b[] = {



PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,


PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,




PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,


PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,

};
int j;



for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain




for (j = 0; j < ck804_num; j++) {
if (busn[j] == 0) {	//sb chain
setup_resource_map_offset(ctrl_devport_conf,
	ARRAY_SIZE(ctrl_devport_conf),




		PCI_DEV(busn[j], 0, 0) , io_base[j]);




		PCI_DEV(busn[j], 0, 0), io_base[j]);
continue;

}
setup_resource_map_offset(ctrl_devport_conf_b,


	ARRAY_SIZE(ctrl_devport_conf_b),


	PCI_DEV(busn[j], 0, 0) , io_base[j]);




			  ARRAY_SIZE(ctrl_devport_conf_b),


			  PCI_DEV(busn[j], 0, 0), io_base[j]);

}

}
-static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
+static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,

		   unsigned *io_base)



{

static const unsigned int ctrl_devport_conf_clear[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,


PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,




PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,


PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,

};
static const unsigned int ctrl_devport_conf_clear_b[] = {



PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,


PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,




PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,


PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,

};
int j;



for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain




for (j = 0; j < ck804_num; j++) {
if (busn[j] == 0) {	//sb chain
setup_resource_map_offset(ctrl_devport_conf_clear,
	ARRAY_SIZE(ctrl_devport_conf_clear),




		PCI_DEV(busn[j], 0, 0) , io_base[j]);




		PCI_DEV(busn[j], 0, 0), io_base[j]);
continue;

}
setup_resource_map_offset(ctrl_devport_conf_clear_b,


	ARRAY_SIZE(ctrl_devport_conf_clear_b),


	PCI_DEV(busn[j], 0, 0) , io_base[j]);




			  ARRAY_SIZE(ctrl_devport_conf_clear_b),


			  PCI_DEV(busn[j], 0, 0), io_base[j]);

}





}



-static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base)
+static void ck804_early_setup(unsigned ck804_num, unsigned *busn,

	      unsigned *io_base)



{

static const unsigned int ctrl_conf_master[] = {


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,





RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,



RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,





RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,






RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,



#ifdef CK804_MB_SETUP

CK804_MB_SETUP


CK804_MB_SETUP



#endif




#if CK804_NUM > 1

RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,



RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,



#endif
#if CK804_NUM == 1

RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,



RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,



#endif

RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,





RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),



RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,





RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,





RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),




+// PANTA	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,

RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),


RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,




-//PANTA		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,

RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),





RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,

RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),



//SYSCTRL



RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),



#if CK804_USE_NIC == 1

RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),


RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),



#endif
#if CK804_USE_ACI == 1

RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),



#endif
#if CK804_NUM > 1

RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),



#endif


};



static const unsigned int ctrl_conf_slave[] = {



RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,



RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,





RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,



RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,





RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,



RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,





RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,





RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,





RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),





RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,

+//PANTA		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,

RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,





RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),






RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),


-//PANTA		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,


RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,

RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),

#if CK804_USE_NIC == 1
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),


#endif


+#if CK804_USE_NIC == 1

RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),


RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),


RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),



+#endif
   };
int j;


for(j=0; j<ck804_num; j++) {
if(busn[j] == 0) {


	setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master),


		PCI_DEV(busn[0],0,0), io_base[0]);




for (j = 0; j < ck804_num; j++) {
if (busn[j] == 0) {


	setup_resource_map_x_offset(ctrl_conf_master,


		ARRAY_SIZE(ctrl_conf_master),


		PCI_DEV(busn[0], 0, 0), io_base[0]);
continue;

}



setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),


	PCI_DEV(busn[j],0,0), io_base[j]);




setup_resource_map_x_offset(ctrl_conf_slave,


			    ARRAY_SIZE(ctrl_conf_slave),


			    PCI_DEV(busn[j], 0, 0), io_base[j]);

}


for(j=0; j< ck804_num; j++) {
// PCI-E (XSPLL) SS table 0x40, x044, 0x48


// SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8


// CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8


setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,


	io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);


setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,


	io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);



-//PANTA		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
-//			io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);

for (j = 0; j < ck804_num; j++) {
/* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */


/* SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8 */


/* CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8 */


setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40,


	       io_base[j] + ANACTRL_IO_BASE + 0x44,


	       io_base[j] + ANACTRL_IO_BASE + 0x48,


	       pcie_ss_tbl, 64);


setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0,


	       io_base[j] + ANACTRL_IO_BASE + 0xb4,


	       io_base[j] + ANACTRL_IO_BASE + 0xb8,


	       sata_ss_tbl, 64);



+//PANTA         setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0,
+//			       io_base[j] + ANACTRL_IO_BASE + 0xc4,
+//			       io_base[j] + ANACTRL_IO_BASE + 0xc8,
+//			       cpu_ss_tbl, 64);
   }




}
static int ck804_early_setup_x(void)
 {

unsigned busn[4];
unsigned io_base[4];
int ck804_num = 0;
int i;


unsigned busn[4], io_base[4];
int i, ck804_num = 0;

I know it is correct to do write code that way, but I wonder each time
if the code actually means i=0, ck804num=0.
...

for(i=0;i<4;i++) {


for (i = 0; i < 4; i++) {
uint32_t id;
device_t dev;


if(i == 0) { // SB chain


	dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);


}


else {


	dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);


}




if (i == 0) // SB chain


	dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0);


else


	dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0);

id = pci_read_config32(dev, PCI_VENDOR_ID);


if(id == 0x005e10de) {




if (id == 0x005e10de) {
busn[ck804_num] = i * 0x40;
io_base[ck804_num] = i * 0x4000;
ck804_num++;



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -13,61 +13,61 @@
 static void ide_init(struct device *dev)
 {
   struct southbridge_nvidia_ck804_config *conf;

/* Enable ide devices so the linux ide driver will work */
uint32_t dword;
uint16_t word;
uint8_t byte;


conf = dev->chip_info;
word = pci_read_config16(dev, 0x50);



/* Ensure prefetch is disabled */


/* Ensure prefetch is disabled. */
word &= ~((1 << 15) | (1 << 13));
if (conf->ide1_enable) {


/* Enable secondary ide interface */


word |= (1<<0);




/* Enable secondary IDE interface. */


word |= (1 << 0);

printk_debug("IDE1 \t");
}
if (conf->ide0_enable) {


/* Enable primary ide interface */


word |= (1<<1);




/* Enable primary IDE interface. */


word |= (1 << 1);

printk_debug("IDE0\n");
}


word |= (1<<12);
word |= (1<<14);


word |= (1 << 12);

word |= (1 << 14);
pci_write_config16(dev, 0x50, word);




byte = 0x20 ; // Latency: 64-->32


byte = 0x20;		/* Latency: 64 --> 32 */
pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);



#if CONFIG_PCI_ROM_RUN == 1
   pci_dev_init(dev);
 #endif



}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
   pci_write_config32(dev, 0x40,

((device & 0xffff) << 16) | (vendor & 0xffff));




	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}



static struct pci_operations lops_pci = {
   .set_subsystem = lpci_set_subsystem,
 };
-static struct device_operations ide_ops  = {
+static struct device_operations ide_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,

.init	     = ide_init,
.scan_bus	 = 0,

-//	.enable	   = ck804_enable,

.ops_pci	  = &lops_pci,


.init             = ide_init,
.scan_bus         = 0,
// .enable        = ck804_enable,

Indentation was better before.
...

.ops_pci          = &lops_pci,

};
static const struct pci_driver ide_driver __pci_driver = {
@@ -75,4 +75,3 @@
   .vendor = PCI_VENDOR_ID_NVIDIA,
   .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE,
 };



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -4,6 +4,7 @@

by yhlu@tyan.com
2006.1 yhlu add dest apicid for IRQ0

*/



#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -44,30 +45,30 @@
 #define INT		(1 << 8)
   /* IO-APIC virtual wire mode configuration */
   /* mask, trigger, polarity, destination, delivery, vector */

{   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
{   1, DISABLED, NONE},
{   2, DISABLED, NONE},
{   3, DISABLED, NONE},
{   4, DISABLED, NONE},
{   5, DISABLED, NONE},
{   6, DISABLED, NONE},
{   7, DISABLED, NONE},
{   8, DISABLED, NONE},
{   9, DISABLED, NONE},
{  10, DISABLED, NONE},
{  11, DISABLED, NONE},
{  12, DISABLED, NONE},
{  13, DISABLED, NONE},
{  14, DISABLED, NONE},
{  15, DISABLED, NONE},
{  16, DISABLED, NONE},
{  17, DISABLED, NONE},
{  18, DISABLED, NONE},
{  19, DISABLED, NONE},
{  20, DISABLED, NONE},
{  21, DISABLED, NONE},
{  22, DISABLED, NONE},
{  23, DISABLED, NONE},


{0,  ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
{1,  DISABLED, NONE},
{2,  DISABLED, NONE},
{3,  DISABLED, NONE},
{4,  DISABLED, NONE},
{5,  DISABLED, NONE},
{6,  DISABLED, NONE},
{7,  DISABLED, NONE},
{8,  DISABLED, NONE},
{9,  DISABLED, NONE},
{10, DISABLED, NONE},
{11, DISABLED, NONE},
{12, DISABLED, NONE},
{13, DISABLED, NONE},
{14, DISABLED, NONE},
{15, DISABLED, NONE},
{16, DISABLED, NONE},
{17, DISABLED, NONE},
{18, DISABLED, NONE},
{19, DISABLED, NONE},
{20, DISABLED, NONE},
{21, DISABLED, NONE},
{22, DISABLED, NONE},
{23, DISABLED, NONE},
/* Be careful and don't write past the end... */

};
@@ -75,23 +76,22 @@
 {
   int i;
   unsigned long value_low, value_high;
-//	unsigned long ioapic_base = 0xfec00000;

/* unsigned long ioapic_base = 0xfec00000; */

I don't get that change. Why did indent use another comment delimiter here?
...
volatile unsigned long *l;
   struct ioapicreg *a = ioapicregvalues;

ioapicregvalues[0].value_high = lapicid()<<(56-32);


ioapicregvalues[0].value_high = lapicid() << (56 - 32);


l = (unsigned long *) ioapic_base;


l = (unsigned long *)ioapic_base;


for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
    i++, a++) {




for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
value_low = l[4];


l[0] = (a->reg *2) + 0x11;




l[0] = (a->reg * 2) + 0x11;

l[4] = a->value_high;
value_high = l[4];


if ((i==0) && (value_low == 0xffffffff)) {




if ((i == 0) && (value_low == 0xffffffff)) {
printk_warning("IO APIC not responding.\n");
return;

}

@@ -117,20 +117,19 @@
   uint8_t byte;
   uint32_t dword;

/* IO APIC initialization */


/* I/O APIC initialization */
byte = pci_read_config8(dev, 0x74);


byte |= (1<<0); // enable APIC


byte |= (1 << 0);	/* Enable APIC. */
pci_write_config8(dev, 0x74, byte);


dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14


dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);	/* 0x14 */
setup_ioapic(dword);


#if 1
   dword = pci_read_config32(dev, 0xe4);

dword |= (1<<23);


dword |= (1 << 23);
pci_write_config32(dev, 0xe4, dword);

#endif



}
static void lpc_slave_init(device_t dev)
@@ -138,132 +137,123 @@
   lpc_common_init(dev);
 }
-static void rom_dummy_write(device_t dev){
+static void rom_dummy_write(device_t dev)
+{
   uint8_t old, new;
   uint8_t *p;
old = pci_read_config8(dev, 0x88);
   new = old | 0xc0;

if (new != old) {


if (new != old)
pci_write_config8(dev, 0x88, new);


}
//  enable write


/* Enable write. */
old = pci_read_config8(dev, 0x6d);
new = old | 0x01;


if (new != old) {


if (new != old)
pci_write_config8(dev, 0x6d, new);


}

/* dummy write */

p = (uint8_t *)0xffffffe0;



/* Dummy write. */
p = (uint8_t *) 0xffffffe0;
old = 0;
*p = old;
old = *p;


//  disable write


/* Disable write. */
old = pci_read_config8(dev, 0x6d);
new = old & 0xfe;


if (new != old) {


if (new != old)
pci_write_config8(dev, 0x6d, new);



}


}



#if 0
 static void enable_hpet(struct device *dev)
 {
   unsigned long hpet_address;

pci_write_config32(dev,0x44, 0xfed00001);
hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
printk_debug("enabling HPET @0x%x\n", hpet_address);


pci_write_config32(dev, 0x44, 0xfed00001);
hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
printk_debug("Enabling HPET @0x%x\n", hpet_address);

}
 #endif
static void lpc_init(device_t dev)
 {

uint8_t byte;
uint8_t byte_old;
int on;
int nmi_option;


uint8_t byte, byte_old;

int on, nmi_option;
lpc_common_init(dev);


#if CK804_CHIP_REV==1

if(dev->bus->secondary!=1) return;


if (dev->bus->secondary != 1)
return;



#endif
#if 0

/* posted memory write enable */


/* Posted memory write enable */
byte = pci_read_config8(dev, 0x46);


pci_write_config8(dev, 0x46, byte | (1<<0));



pci_write_config8(dev, 0x46, byte | (1 << 0));

#endif

/* power after power fail */


/* power after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;


if (!on) {


if (!on)
byte |= 0x40;


}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk_info("set power %s after power fail\n", on?"on":"off");


printk_info("set power %s after power fail\n", on ? "on" : "off");


/* Throttle the CPU speed down for testing */


/* Throttle the CPU speed down for testing. */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");


if(on) {


if (on) {
uint16_t pm10_bar;
uint32_t dword;


pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);


outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));




pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);


outl(((on << 1) + 0x10), (pm10_bar + 0x10));

dword = inl(pm10_bar + 0x10);


on = 8-on;




on = 8 - on;

printk_debug("Throttling CPU %2d.%1.1d percent.\n",


		(on*12)+(on>>1),(on&1)*5);




	     (on * 12) + (on >> 1), (on & 1) * 5);

}




#if 0
 // default is enabled

/* Enable Port 92 fast reset */


/* Enable Port 92 fast reset. */
byte = pci_read_config8(dev, 0xe8);
byte |= ~(1 << 3);
pci_write_config8(dev, 0xe8, byte);

#endif

/* Enable Error reporting */
/* Set up sync flood detected */


/* Enable Error reporting. */
/* Set up sync flood detected. */
byte = pci_read_config8(dev, 0x47);
byte |= (1 << 1);
pci_write_config8(dev, 0x47, byte);


/* Set up NMI on errors */
byte = inb(0x70); // RTC70


/* Set up NMI on errors. */
byte = inb(0x70);		/* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {


byte &= ~(1 << 7); /* set NMI */




byte &= ~(1 << 7); /* Set NMI. */

} else {


byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW




byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */

}


if( byte != byte_old) {


if (byte != byte_old)
outb(0x70, byte);


}

/* Initialize the real time clock */



/* Initialize the real time clock (RTC). */
rtc_init(0);


/* Initialize isa dma */


/* Initialize ISA DMA. */
isa_dma_init();


/* Initialize the High Precision Event Timers */

-//	enable_hpet(dev);

/* Initialize the High Precision Event Timers (HPET). */

/* enable_hpet(dev); */
rom_dummy_write(dev);





}
static void ck804_lpc_read_resources(device_t dev)
@@ -271,43 +261,43 @@
   struct resource *res;
   unsigned long index;

/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP


/* Get the normal PCI resources of this device. */
/* We got one for APIC, or one more for TRAP. */
pci_dev_read_resources(dev);


/* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */
for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.


/* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
for (index = 0x60; index <= 0x68; index += 4)	/* We got another 3. */
pci_get_resource(dev, index);


}
compact_resources(dev);

/* Add an extra subtractive resource for both memory and I/O */



/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));


res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;


res->flags =

   IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;


res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));



res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;



res->flags =
   IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;



}
/**


@brief Enable resources for children devices





Enable resources for children devices.






@param dev the device whos children's resources are to be enabled







This function is call by the global enable_resources() indirectly via the





This function is called by the global enable_resources() indirectly via the
device_operation::enable_resources() method of devices.

Indirect mutual recursion:
 enable_childrens_resources() -> enable_resources()


 enable_resources() -> device_operation::enable_resources()


 device_operation::enable_resources() -> enable_children_resources()









@param dev The device whose children's resources are to be enabled.

*/

static void ck804_lpc_enable_childrens_resources(device_t dev)
 {
   unsigned link;
   uint32_t reg, reg_var[4];

int i;
int var_num = 0;


int i, var_num = 0;
reg = pci_read_config32(dev, 0xa0);


@@ -315,44 +305,49 @@
   	device_t child;
   	for (child = dev->link[link].children; child; child = child->sibling) {
   		enable_resources(child);

	if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {


		for(i=0;i<child->resources;i++) {




	if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {


		for (i = 0; i < child->resources; i++) {
		struct resource *res;




			unsigned long base, end; // don't need long long




			unsigned long base, end;	// don't need long long
		res = &child->resource[i];




			if(!(res->flags & IORESOURCE_IO)) continue;




			if (!(res->flags & IORESOURCE_IO))


				continue;
		base = res->base;
		end = resource_end(res);




			printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);


			switch(base) {


			case 0x3f8: // COM1


				reg |= (1<<0); 	break;


			case 0x2f8: // COM2


				reg |= (1<<1);  break;


			case 0x378: // Parallal 1


				reg |= (1<<24); break;


			case 0x3f0: // FD0


				reg |= (1<<20); break;


			case 0x220:  // Aduio 0


				reg |= (1<<8); 	break;


			case 0x300:  // Midi 0


				reg |= (1<<12);	break;




			printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n", dev_path(child), base, end);


			switch (base) {


			case 0x3f8:	// COM1


				reg |= (1 << 0);


				break;


			case 0x2f8:	// COM2


				reg |= (1 << 1);


				break;


			case 0x378:	// Parallel 1


				reg |= (1 << 24);


				break;


			case 0x3f0:	// FD0


				reg |= (1 << 20);


				break;


			case 0x220:	// Audio 0


				reg |= (1 << 8);


				break;


			case 0x300:	// Midi 0


				reg |= (1 << 12);


				break;
		}




			if( base == 0x290 || base >= 0x400) {


				if(var_num>=4) continue; // only 4 var ; compact them ?


				reg |= (1<<(28+var_num));


				reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);




			if (base == 0x290 || base >= 0x400) {


				if (var_num >= 4)


					continue;	// only 4 var ; compact them ?


				reg |= (1 << (28 + var_num));


				reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
		}
	}
}

}
}
pci_write_config32(dev, 0xa0, reg);


for(i=0;i<var_num;i++) {
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);


}




for (i = 0; i < var_num; i++)
pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);



}
static void ck804_lpc_enable_resources(device_t dev)
@@ -364,22 +359,23 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
   pci_write_config32(dev, 0x40,

((device & 0xffff) << 16) | (vendor & 0xffff));




	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}
static struct pci_operations lops_pci = {
   .set_subsystem = lpci_set_subsystem,
 };
-static struct device_operations lpc_ops  = {
+static struct device_operations lpc_ops = {
   .read_resources   = ck804_lpc_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = ck804_lpc_enable_resources,
   .init             = lpc_init,
   .scan_bus         = scan_static_bus,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Indentation.
...
.ops_pci          = &lops_pci,
 };



static const struct pci_driver lpc_driver __pci_driver = {
   .ops    = &lpc_ops,
   .vendor = PCI_VENDOR_ID_NVIDIA,
@@ -399,12 +395,12 @@
   .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 };
 #else
-static struct device_operations lpc_slave_ops  = {
+static struct device_operations lpc_slave_ops = {
   .read_resources   = ck804_lpc_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
   .init             = lpc_slave_init,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Same here.
...
.ops_pci          = &lops_pci,
 };
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@

Copyright 2004 Tyan Computer
by yhlu@tyan.com

*/



#include <console/console.h>
 #include <device/device.h>
 #include <device/smbus.h>
@@ -11,21 +12,16 @@
 #include <arch/io.h>
 #include "ck804.h"



static void nic_init(struct device *dev)
 {

uint32_t dword, old;
uint32_t mac_h, mac_l;


uint32_t dword, old, mac_h, mac_l;
int eeprom_valid = 0;
struct southbridge_nvidia_ck804_config *conf;


static uint32_t nic_index = 0;

uint8_t *base;
 struct resource *res;
res = find_resource(dev, 0x10);

base = res->base;


#define NvRegPhyInterface  0xC0
@@ -36,37 +32,37 @@
   old = dword = pci_read_config32(dev, 0x30);
   dword &= ~(0xf);
   dword |= 0xf;

if(old != dword) {
pci_write_config32(dev, 0x30 , dword);


}


if (old != dword)

pci_write_config32(dev, 0x30, dword);


conf = dev->chip_info;



if(conf->mac_eeprom_smbus != 0) {

-//      read MAC address from EEPROM at first

if (conf->mac_eeprom_smbus != 0) {
/* Read MAC address from EEPROM at first. */

struct device *dev_eeprom;


dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);




dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,


			   conf->mac_eeprom_addr);





if(dev_eeprom) {


//	if that is valid we will use that




if (dev_eeprom) {


	/* If that is valid we will use that. */
unsigned char dat[6];




	int status;


	int i;


	for(i=0;i<6;i++) {




	int i, status;


	for (i = 0; i < 6; i++) {
	status = smbus_read_byte(dev_eeprom, i);




		if(status < 0) break;




		if (status < 0)


			break;
	dat[i] = status & 0xff;
}




	if(status >= 0) {




	if (status >= 0) {
	mac_l = 0;




		for(i=3;i>=0;i--) {




		for (i = 3; i >= 0; i--) {
		mac_l <<= 8;
		mac_l += dat[i];
	}




		if(mac_l != 0xffffffff) {




		if (mac_l != 0xffffffff) {
		mac_l += nic_index;
		mac_h = 0;




			for(i=5;i>=4;i--) {




			for (i = 5; i >= 4; i--) {
			mac_h <<= 8;
			mac_h += dat[i];
		}



@@ -75,21 +71,22 @@
   		}
   	}
   }
-//	if that is invalid we will read that from romstrap

if(!eeprom_valid) {



/* If that is invalid we will read that from romstrap. */
if (!eeprom_valid) {
unsigned long mac_pos;


mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds




mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */

mac_l = readl(mac_pos) + nic_index;
mac_h = readl(mac_pos + 4);
}

#if 1
-//      set that into NIC MMIO

/* Set that into NIC MMIO. */

#define NvRegMacAddrA  0xA8
 #define NvRegMacAddrB  0xAC
   writel(mac_l, base + NvRegMacAddrA);
   writel(mac_h, base + NvRegMacAddrB);
 #else
-//	set that into NIC

/* Set that into NIC. */
pci_write_config32(dev, 0xa8, mac_l);
pci_write_config32(dev, 0xac, mac_h);

#endif
@@ -97,35 +94,36 @@
   nic_index++;
#if CONFIG_PCI_ROM_RUN == 1

pci_dev_init(dev);// it will init option rom


pci_dev_init(dev);	/* It will init Option ROM. */

#endif



}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
   pci_write_config32(dev, 0x40,

((device & 0xffff) << 16) | (vendor & 0xffff));




	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}
static struct pci_operations lops_pci = {
   .set_subsystem = lpci_set_subsystem,
 };
-static struct device_operations nic_ops  = {
+static struct device_operations nic_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
   .init             = nic_init,
   .scan_bus         = 0,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Indentation.
...
.ops_pci          = &lops_pci,
 };



static const struct pci_driver nic_driver __pci_driver = {
   .ops    = &nic_ops,
   .vendor = PCI_VENDOR_ID_NVIDIA,
   .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC,
 };



static const struct pci_driver nic_bridge_driver __pci_driver = {
   .ops    = &nic_ops,
   .vendor = PCI_VENDOR_ID_NVIDIA,
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -12,70 +12,72 @@
static void pci_init(struct device *dev)
 {

uint32_t dword;

#if CONFIG_PCI_64BIT_PREF_MEM == 1
   device_t pci_domain_dev;
   struct resource *mem1, *mem2;
 #endif

/* System error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */


dword |= (1 << 8);	/* System error enable */
dword |= (1 << 30);	/* Clear possible errors */
pci_write_config32(dev, 0x04, dword);

#if 0
   word = pci_read_config16(dev, 0x48);

word |= (1<<0); /* MRL2MRM */
word |= (1<<2); /* MR2MRM */


word |= (1 << 0);	/* MRL2MRM */
word |= (1 << 2);	/* MR2MRM */
pci_write_config16(dev, 0x48, word);

#endif
#if 1
   dword = pci_read_config32(dev, 0x4c);

dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/


dword |= 0x00440000;	/* TABORT_SER_ENABLE Park Last Enable. */
pci_write_config32(dev, 0x4c, dword);

#endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1
   pci_domain_dev = dev->bus->dev;

while(pci_domain_dev) {
if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;




while (pci_domain_dev) {
if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)


	break;

pci_domain_dev = pci_domain_dev->bus->dev;
}


if(!pci_domain_dev) return; // impossiable
mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
mem2 = find_resource(pci_domain_dev, 2); // mem
if(mem1->base > mem2->base) {
dword = mem2->base  & (0xffff0000UL);




if (!pci_domain_dev)
return;		/* Impossible */



mem1 = find_resource(pci_domain_dev, 1);	// prefmem, it could be 64bit
mem2 = find_resource(pci_domain_dev, 2);	// mem
if (mem1->base > mem2->base) {
dword = mem2->base & (0xffff0000UL);

printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
} else {


dword = mem1->base  & (0xffff0000UL);


printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);




dword = mem1->base & (0xffff0000UL);


printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n",


	     mem1->base);

}

#else
   dword = dev_root.resource[1].base & (0xffff0000UL);

printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);


printk_debug("dev_root mem base = 0x%010Lx\n",
     dev_root.resource[1].base);



#endif
printk_debug("[0x50] <-- 0x%08x\n", dword);

pci_write_config32(dev, 0x50, dword); //TOM



pci_write_config32(dev, 0x50, dword);	/* TOM */

}
static struct pci_operations lops_pci = {
   .set_subsystem = 0,
 };
-static struct device_operations pci_ops  = {
+static struct device_operations pci_ops = {
   .read_resources   = pci_bus_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_bus_enable_resources,
   .init             = pci_init,
   .scan_bus         = pci_scan_bridge,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Indentation.
...
.ops_pci          = &lops_pci,
 };
@@ -84,4 +86,3 @@
   .vendor = PCI_VENDOR_ID_NVIDIA,
   .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI,
 };



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -12,29 +12,26 @@
static void pcie_init(struct device *dev)
 {


/* Enable pci error detecting */
uint32_t dword;

/* System error enable */



/* Enable PCI error detecting. */
dword = pci_read_config32(dev, 0x04);


dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */


dword |= (1 << 8);	/* System error enable */
dword |= (1 << 30);	/* Clear possible errors */
pci_write_config32(dev, 0x04, dword);




}
static struct pci_operations lops_pci = {
   .set_subsystem = 0,
 };
-static struct device_operations pcie_ops  = {
+static struct device_operations pcie_ops = {
   .read_resources   = pci_bus_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_bus_enable_resources,
   .init             = pcie_init,
   .scan_bus         = pci_scan_bridge,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Indentation.
...
.ops_pci          = &lops_pci,
 };
@@ -43,4 +40,3 @@
   .vendor = PCI_VENDOR_ID_NVIDIA,
   .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E,
 };



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -15,7 +15,7 @@
 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
 {
   unsigned addr;

addr = (dev>>4) | where;


addr = (dev >> 4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);

}
@@ -23,7 +23,7 @@
 static unsigned pci_read_config32(device_t dev, unsigned where)
 {
   unsigned addr;

addr = (dev>>4) | where;


addr = (dev >> 4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);

}
@@ -33,8 +33,7 @@
 void hard_reset(void)
 {
   set_bios_reset();

/* Try rebooting through port 0xcf9 */
outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
 	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);




/* Try rebooting through port 0xcf9. */
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);

}



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@

Copyright 2004 Tyan Computer
by yhlu@tyan.com

*/



#include <console/console.h>
 #include <device/device.h>
 #include <delay.h>
@@ -10,7 +11,6 @@
 #include <device/pci_ops.h>
 #include "ck804.h"



static void sata_com_reset(struct device *dev, unsigned reset)
 // reset = 1 : reset
 // reset = 0 : clear
@@ -23,12 +23,12 @@
printk_debug("base = %08x\r\n", base);

if(reset) {
       *(base + 4) = 0xffffffff;


       *(base + 0x44) = 0xffffffff;




if (reset) {
*(base + 4) = 0xffffffff;


*(base + 0x44) = 0xffffffff;

}


dword = *(base +8);


dword = *(base + 8);
dword &= ~(0xf);
dword |= reset;

@@ -42,87 +42,89 @@
   *(base + 0x48) = dword;
 #endif

if(reset) return;


if (reset)
return;





dword = *(base+ 0);
printk_debug("*(base+0)=%08x\r\n",dword);
if(dword == 0x113) {
loop = 200000;// 2




dword = *(base + 0);
printk_debug("*(base+0)=%08x\r\n", dword);
if (dword == 0x113) {
loop = 200000;	// 2

do {


        dword = *(base + 4);


	if((dword & 0x10000)!=0) break;




	dword = *(base + 4);


	if ((dword & 0x10000) != 0)


		break;
udelay(10);




} while (--loop>0);


printk_debug("loop=%d, *(base+4)=%08x\r\n",loop,  dword);




} while (--loop > 0);


printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword);

}


dword = *(base+ 0x40);
printk_debug("*(base+0x40)=%08x\r\n",dword);
if(dword == 0x113) {
       loop = 200000;//2


       do {


        dword = *(base + 0x44);


        if((dword & 0x10000)!=0) break;




dword = *(base + 0x40);
printk_debug("*(base+0x40)=%08x\r\n", dword);
if (dword == 0x113) {
loop = 200000;	//2


do {


	dword = *(base + 0x44);


	if ((dword & 0x10000) != 0)


		break;
udelay(10);




} while (--loop>0);


printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop,  dword);




} while (--loop > 0);


printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword);

}

}
static void sata_init(struct device *dev)
 {

uint32_t dword;


struct southbridge_nvidia_ck804_config *conf;


struct southbridge_nvidia_ck804_config *conf;
conf = dev->chip_info;
dword = pci_read_config32(dev, 0x50);

/* Ensure prefetch is disabled */



/* Ensure prefetch is disabled. */
dword &= ~((1 << 15) | (1 << 13));
if (conf->sata1_enable) {


       /* Enable secondary SATA interface */


       dword |= (1<<0);


       printk_debug("SATA S \t");




/* Enable secondary SATA interface. */


dword |= (1 << 0);


printk_debug("SATA S \t");

}
if (conf->sata0_enable) {


       /* Enable primary SATA interface */


       dword |= (1<<1);


       printk_debug("SATA P \n");




/* Enable primary SATA interface. */


dword |= (1 << 1);


printk_debug("SATA P \n");

}

#if 0
-//	write back

dword |= (1<<12);
dword |= (1<<14);


/* Write back */
dword |= (1 << 12);
dword |= (1 << 14);

#endif
#if 0
-//	ADMA

dword |= (1<<16);
dword |= (1<<17);


/* ADMA */
dword |= (1 << 16);
dword |= (1 << 17);

#endif
#if 1
-//DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT.

dword &= ~(0x1f<<24);
dword |= (0x15<<24);


/* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */
dword &= ~(0x1f << 24);
dword |= (0x15 << 24);

#endif
   pci_write_config32(dev, 0x50, dword);
#if 0
-//SLUMBER_DURING_D3.

/* SLUMBER_DURING_D3 */
dword = pci_read_config32(dev, 0x7c);


dword &=  ~(1<<4);


dword &= ~(1 << 4);
pci_write_config32(dev, 0x7c, dword);
dword = pci_read_config32(dev, 0xd0);



dword &=  ~(0xff<<24);
dword |= (0x68<<24);


dword &= ~(0xff << 24);

dword |= (0x68 << 24);
pci_write_config32(dev, 0xd0, dword);
dword = pci_read_config32(dev, 0xe0);



dword &=  ~(0xff<<24);
dword |= (0x68<<24);


dword &= ~(0xff << 24);
dword |= (0x68 << 24);
pci_write_config32(dev, 0xe0, dword);

#endif
@@ -132,11 +134,11 @@
#if 0
   dword = pci_read_config32(dev, 0xac);

dword &= ~((1<<13)|(1<<14));
dword |= (1<<13)|(0<<14);


dword &= ~((1 << 13) | (1 << 14));
dword |= (1 << 13) | (0 << 14);
pci_write_config32(dev, 0xac, dword);


sata_com_reset(dev, 1); // for discover some s-atapi device


sata_com_reset(dev, 1);	/* For discover some s-atapi device. */

#endif
}
@@ -144,17 +146,18 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
   pci_write_config32(dev, 0x40,

       ((device & 0xffff) << 16) | (vendor & 0xffff));




	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}



static struct pci_operations lops_pci = {
   .set_subsystem = lpci_set_subsystem,
 };
-static struct device_operations sata_ops  = {
+static struct device_operations sata_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,
.init             = sata_init,
.scan_bus         = 0,
.ops_pci          = &lops_pci,

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@

Copyright 2004 Tyan Computer
by yhlu@tyan.com

*/



#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -68,6 +69,7 @@
return do_smbus_write_byte(res->base, device, address, val);
 }



static struct smbus_bus_operations lops_smbus_bus = {
   .recv_byte  = lsmbus_recv_byte,
   .send_byte  = lsmbus_send_byte,
@@ -78,25 +80,26 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
   pci_write_config32(dev, 0x40,

((device & 0xffff) << 16) | (vendor & 0xffff));




	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}
static struct pci_operations lops_pci = {
   .set_subsystem = lpci_set_subsystem,
 };



static struct device_operations smbus_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
   .init             = 0,
   .scan_bus         = scan_static_bus,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Indentation.
...
.ops_pci          = &lops_pci,
   .ops_smbus_bus    = &lops_smbus_bus,
 };



static const struct pci_driver smbus_driver __pci_driver = {
   .ops    = &smbus_ops,
   .vendor = PCI_VENDOR_ID_NVIDIA,
   .device = PCI_DEVICE_ID_NVIDIA_CK804_SM,
 };



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@

Copyright 2004 Tyan Computer
by yhlu@tyan.com

*/



#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -9,34 +10,41 @@
 #include <device/pci_ops.h>
 #include "ck804.h"
-static void usb1_init(struct device *dev) {

struct southbridge_nvidia_ck804_config const * conf=dev->chip_info;

+static void usb1_init(struct device *dev)
+{

struct southbridge_nvidia_ck804_config const *conf = dev->chip_info;
if (conf->usb1_hc_reset) {


//Somehow the warm reset does not really resets the USB controller.


//Later, during boot, when the Bus Master bit is set, the USB


//controller trashes the memory, causing weird misbehavior.


//Was detected on Sun Ultra40, where mptable was damaged.


uint32_t bar0=pci_read_config32(dev,0x10);


uint32_t* regs=(uint32_t*)(bar0&~0xfff);


regs[2]|=1;	//OHCI USB HCCommandStatus Register, HostControllerReset bit




/*


 * Somehow the warm reset does not really reset the USB


 * controller. Later, during boot, when the Bus Master bit is


 * set, the USB controller trashes the memory, causing weird


 * misbehavior. Was detected on Sun Ultra40, where mptable


 * was damaged.


 */


uint32_t bar0 = pci_read_config32(dev, 0x10);


uint32_t *regs = (uint32_t *) (bar0 & ~0xfff);



/* OHCI USB HCCommandStatus Register, HostControllerReset bit */


regs[2] |= 1;

}

}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
   pci_write_config32(dev, 0x40,

((device & 0xffff) << 16) | (vendor & 0xffff));




	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}



static struct pci_operations lops_pci = {
   .set_subsystem = lpci_set_subsystem,
 };
-static struct device_operations usb_ops  = {
+static struct device_operations usb_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
   .init             = usb1_init,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Undo the indentation change, please.
...
.scan_bus         = 0,
   .ops_pci          = &lops_pci,
 };
@@ -46,4 +54,3 @@
   .vendor = PCI_VENDOR_ID_NVIDIA,
   .device = PCI_DEVICE_ID_NVIDIA_CK804_USB,
 };



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@

Copyright 2004 Tyan Computer
by yhlu@tyan.com

*/



#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -11,7 +12,6 @@
static void usb2_init(struct device *dev)
 {

uint32_t dword;
 dword = pci_read_config32(dev, 0xf8);
 dword |= 40;

@@ -21,18 +21,19 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
   pci_write_config32(dev, 0x40,

((device & 0xffff) << 16) | (vendor & 0xffff));




	   ((device & 0xffff) << 16) | (vendor & 0xffff));



}



static struct pci_operations lops_pci = {
   .set_subsystem = lpci_set_subsystem,
 };
-static struct device_operations usb2_ops  = {
+static struct device_operations usb2_ops = {
   .read_resources   = pci_dev_read_resources,
   .set_resources    = pci_dev_set_resources,
   .enable_resources = pci_dev_enable_resources,
   .init             = usb2_init,
-//	.enable           = ck804_enable,

// .enable        = ck804_enable,

Undo the indentation change, please.
...
.scan_bus         = 0,
   .ops_pci          = &lops_pci,
 };
-- 
http://www.hailfinger.org/



    

Re: [coreboot] r3631 - trunk/coreboot-v2/src/southbridge/nvidia/ck804

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c