This patch makes ITE SuperI/O probing/dumping a little bit more generic, fixes minor codingstyle issues and prepares the table for supporting more chips of the ITE IT87xx SuperI/O family.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
--- LinuxBIOSv2/util/probe_superio/probe_superio.c (Revision 2749) +++ LinuxBIOSv2/util/probe_superio/probe_superio.c (Arbeitskopie) @@ -35,22 +35,22 @@
unsigned char regval(unsigned short port, unsigned char reg) { outb(reg, port); - return inb(port+1); + return inb(port + 1); }
void regwrite(unsigned short port, unsigned char reg, unsigned char val) { outb(reg, port); - outb(val, port+1); + outb(val, port + 1); }
void dump_ns8374(unsigned short port) { - printf("Enables: 21=%02x, 22=%02x, 23=%02x, 24=%02x, 26=%02x\n", - regval(port,0x21), regval(port,0x22), - regval(port,0x23), regval(port,0x24), regval(port,0x26)); + printf("Enables: 21=%02x, 22=%02x, 23=%02x, 24=%02x, 26=%02x\n", + regval(port, 0x21), regval(port, 0x22), regval(port, 0x23), + regval(port, 0x24), regval(port, 0x26)); printf("SMBUS at %02x\n", regval(port, 0x2a)); /* check COM1. This is all we care about at present. */ - printf("COM 1 is Globally %s\n", regval(port,0x26)&8 ? "disabled" : "enabled"); + printf("COM 1 is Globally %s\n", regval(port, 0x26) & 8 ? "disabled" : "enabled"); /* select com1 */ regwrite(port, 0x07, 0x03); printf("COM 1 is locally %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); @@ -77,11 +77,11 @@ printf ("Fintek F71872\n"); break; default: - printf ("Unknown Fintek SuperIO: did=0x%04x\n",did); + printf ("Unknown Fintek SuperI/O: did=0x%04x\n", did); return; }
- printf("Flash write is %s.\n", regval(port, 0x28)&0x80 ? "enabled" : "disabled"); + printf("Flash write is %s.\n", regval(port, 0x28) & 0x80 ? "enabled" : "disabled"); printf("Flash control is 0x%04x.\n", regval(port, 0x28)); printf("27=%02x\n", regval(port, 0x27)); printf("29=%02x\n", regval(port, 0x29)); @@ -92,27 +92,27 @@ regwrite(port, 0x07, 0x01); printf("UART1 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART1 base=%02x%02x, irq=%02x, mode=%s\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, - regval(port, 0xf0)&0x10 ? "RS485":"RS232"); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f, + regval(port, 0xf0) & 0x10 ? "RS485":"RS232");
/* select UART 2 */ regwrite(port, 0x07, 0x02); printf("UART2 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART2 base=%02x%02x, irq=%02x, mode=%s\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, - regval(port, 0xf0)&0x10 ? "RS485":"RS232"); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f, + regval(port, 0xf0) & 0x10 ? "RS485":"RS232");
/* select Parport */ regwrite(port, 0x07, 0x03); printf("PARPORT is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("PARPORT base=%02x%02x, irq=%02x\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f);
/* select hw monitor */ regwrite(port, 0x07, 0x04); printf("HW monitor is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("HW monitor base=%02x%02x, irq=%02x\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f);
/* select gpio */ regwrite(port, 0x07, 0x05); @@ -129,25 +129,39 @@
}
-//End Of Table +/* End Of Table */ #define EOT -1 -//NO LDN needed +/* NO LDN needed */ #define NOLDN -2 -//Not Available +/* Not Available */ #define NANA -3 -//Biggest LDN +/* Maximum Name Length */ +#define MAXNAMELEN 20 +/* Biggest LDN */ #define MAXLDN 0xa -//MAXimum NUMber of Indexes +/* biggestLDN + 0 + NOLDN + EOT */ +#define LDNSIZE MAXLDN + 3 +/* MAXimum NUMber of Indexes */ #define MAXNUMIDX 70 +#define IDXSIZE MAXNUMIDX + 1 + const static struct ite_registers { - signed short superio_id; //yes, it should be unsigned, but then EOT has to be positive + /* yes, superio_id should be unsigned, but EOT has to be negative */ + signed short superio_id; + char name[MAXNAMELEN]; struct ite_ldnidx { signed short ldn; - signed short idx[MAXNUMIDX+1]; - signed short def[MAXNUMIDX+1]; - } ldn[MAXLDN+3]; //biggestLDN+0+NOLDN+EOT + signed short idx[IDXSIZE]; + signed short def[IDXSIZE]; + } ldn[LDNSIZE]; } ite_reg_table[] = { - {0x8712,{ + {0x8702, "IT8702", { + {EOT}}}, + {0x8705, "IT8705 or IT8700", { + {EOT}}}, + {0x8710, "IT8710", { + {EOT}}}, + {0x8712, "IT8712", { {NOLDN, {0x07,0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {NANA,0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, @@ -164,8 +178,10 @@ {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, {0x4, - {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, - {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00,0x00,NANA,NANA,EOT}}, + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3, + 0xf4,0xf5,0xf6,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00, + 0x00,NANA,NANA,EOT}}, {0x5, {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, @@ -173,8 +189,18 @@ {0x30,0x70,0x71,0xf0,EOT}, {0x00,0x0c,0x02,0x00,EOT}}, {0x7, - {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, - {0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x00,EOT}}, + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62, + 0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1, + 0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd, + 0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc, + 0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, + {0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x30,0x38,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x00,EOT}}, {0x8, {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, @@ -185,6 +211,10 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, + {0x8716, "IT8716", { + {EOT}}}, + {0x8718, "IT8718", { + {EOT}}}, {EOT} };
@@ -204,73 +234,65 @@ 0x8708 -> IT8708 0x8710 -> IT8710 0x8712 -> IT8712 - 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8716 -> IT8716 0x8718 -> IT8718 - 0x8726 does not exist according to datasheet, but experience differs + 0x8726 -> IT8726 (datasheet wrongly says 0x8716) */ switch(id) { - case 0x8702: - printf ("IT8702\n"); - break; - case 0x8705: - printf ("IT8700 or IT8705\n"); - break; - case 0x8710: - printf ("IT8710\n"); - break; - case 0x8712: - printf ("IT8712\n"); - for (i=0;; i++) { - if (ite_reg_table[i].superio_id == EOT) + case 0x8702: + case 0x8705: + case 0x8710: + case 0x8712: + case 0x8716: + case 0x8718: + for (i=0;; i++) { + if (ite_reg_table[i].superio_id == EOT) + break; + if ((unsigned short)ite_reg_table[i].superio_id != id) + continue; + printf ("%s\n", ite_reg_table[i].name); + for (j=0;; j++) { + if (ite_reg_table[i].ldn[j].ldn == EOT) break; - if ((unsigned short)ite_reg_table[i].superio_id != id) - continue; - for (j=0;; j++) { - if (ite_reg_table[i].ldn[j].ldn == EOT) + if (ite_reg_table[i].ldn[j].ldn != NOLDN) { + printf("switching to LDN 0x%01x\n", + ite_reg_table[i].ldn[j].ldn); + regwrite(port, 0x07, + ite_reg_table[i].ldn[j].ldn); + } + idx = ite_reg_table[i].ldn[j].idx; + printf("idx "); + for (k=0;; k++) { + if (idx[k] == EOT) break; - if (ite_reg_table[i].ldn[j].ldn != NOLDN) { - printf("switching to LDN 0x%01x\n", ite_reg_table[i].ldn[j].ldn); - regwrite(port, 0x07, ite_reg_table[i].ldn[j].ldn); - } - idx = ite_reg_table[i].ldn[j].idx; - printf("idx "); - for (k=0;; k++) { - if (idx[k] == EOT) - break; + printf("%02x ", idx[k]); + } + printf("\nval "); + for (k=0;; k++) { + if (idx[k] == EOT) + break; + printf("%02x ", regval(port, idx[k])); + } + printf("\ndef "); + idx = ite_reg_table[i].ldn[j].def; + for (k=0;; k++) { + if (idx[k] == EOT) + break; + if (idx[k] == NANA) + printf("NA "); + else printf("%02x ", idx[k]); - } - printf("\nval "); - for (k=0;; k++) { - if (idx[k] == EOT) - break; - printf("%02x ", regval(port, idx[k])); - } - printf("\ndef "); - idx = ite_reg_table[i].ldn[j].def; - for (k=0;; k++) { - if (idx[k] == EOT) - break; - if (idx[k] == NANA) - printf("NA "); - else - printf("%02x ", idx[k]); - } - printf("\n"); } + printf("\n"); + } - } - break; - case 0x8716: - printf ("IT8716 or IT8726\n"); - break; - case 0x8718: - printf ("IT8718\n"); - break; - default: - printf ("unknown ITE chip, id=%04x\n", id); - for (i=0x20; i<=0x24; i++) - printf("index %02x=%02x\n", i, regval(port, i)); - break; + } + break; + default: + printf ("unknown ITE chip, id=%04x\n", id); + for (i=0x20; i<=0x24; i++) + printf("index %02x=%02x\n", i, regval(port, i)); + break; } }
@@ -280,15 +302,15 @@ outb(0x20, port); if (inb(port) != 0x20) { if (inb(port) == 0xff ) - printf ("No SuperIO chip found at 0x%04x\n", port); + printf ("No SuperI/O chip found at 0x%04x\n", port); else printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", - port, inb(port), inb(port+1)); + port, inb(port), inb(port + 1)); return; } - id = inb(port+1); + id = inb(port + 1);
- printf("SuperIO found at 0x%02x: id = 0x%02x\n", port, id); + printf("SuperI/O found at 0x%02x: id = 0x%02x\n", port, id); if (id == 0xff) return;
@@ -312,40 +334,39 @@ probe_idregs_fintek(unsigned short port){ unsigned int vid, did, success = 0;
- // Enable configuration sequence (Fintek uses this for example) - // Older ITE chips have the same enable sequence + /* Enable configuration sequence (Fintek uses this for example) + Older ITE chips have the same enable sequence */ outb(0x87, port); outb(0x87, port);
- // outb(0x20, port); if (inb(port) != 0x20) { if (inb(port) == 0xff ) printf ("No SuperIO chip found at 0x%04x\n", port); else printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", - port, inb(port), inb(port+1)); + port, inb(port), inb(port + 1)); return; } - did = inb(port+1); + did = inb(port + 1);
- did = did|(regval(port, 0x21)<<8); + did |= (regval(port, 0x21)<<8);
vid = regval(port, 0x23); - vid = vid|(regval(port, 0x24)<<8); + vid |= (regval(port, 0x24)<<8);
printf("SuperIO found at 0x%02x: vid=0x%04x/did=0x%04x\n", port, vid, did);
if (vid == 0xff || vid == 0xffff) return;
- // printf("%s\n", familyid[id]); + /* printf("%s\n", familyid[id]); */ switch(did) { - case 0x0887: // reversed for ITE8708 - case 0x1087: // reversed for ITE8710 + case 0x0887: /* pseudoreversed for ITE8708 */ + case 0x1087: /* pseudoreversed for ITE8710 */ success = 1; dump_ite(port, ((did & 0xff) << 8) | ((did & 0xff00) >> 8)); - // disable configuration + /* disable configuration */ regwrite(port, 0x02, 0x02); break; default: @@ -362,7 +383,7 @@ if (!success) printf("no dump for vid 0x%04x, did 0x%04x\n", vid, did);
- // disable configuration (for Fintek, doesn't hurt ITE) + /* disable configuration (for Fintek, doesn't hurt ITE) */ outb(0xaa, port); }
@@ -370,12 +391,12 @@ probe_idregs_ite(unsigned short port){ unsigned int id, chipver;
- // Enable configuration sequence (ITE uses this for newer IT87[012]x) - // IT871[01] uses 0x87, 0x87 -> fintek detection should handle it - // IT8761 uses 0x87, 0x61, 0x55, 0x55/0xaa - // IT86xx series uses different ports - // IT8661 uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes - // IT8673 uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes + /* Enable configuration sequence (ITE uses this for newer IT87[012]x) + IT871[01] uses 0x87, 0x87 -> fintek detection should handle it + IT8761 uses 0x87, 0x61, 0x55, 0x55/0xaa + IT86xx series uses different ports + IT8661 uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes + IT8673 uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes */ outb(0x87, port); outb(0x01, port); outb(0x55, port); @@ -384,23 +405,23 @@ else outb(0xAA, port);
- // Read Chip ID Byte 1 + /* Read Chip ID Byte 1 */ id = regval(port, 0x20); if (id != 0x87) { if (inb(port) == 0xff ) printf ("No SuperIO chip found at 0x%04x\n", port); else printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", - port, inb(port), inb(port+1)); + port, inb(port), inb(port + 1)); return; }
id <<= 8;
- // Read Chip ID Byte 2 + /* Read Chip ID Byte 2 */ id |= regval(port, 0x21);
- // Read Chip Version, only bit 3..0 for all IT87xx + /* Read Chip Version, only bit 3..0 for all IT87xx */ chipver = regval(port, 0x22) & 0x0f;
/* ID Mapping Table @@ -410,26 +431,27 @@ 0x8705 -> IT8700 or IT8705 0x8710 -> IT8710 0x8712 -> IT8712 - 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8716 -> IT8716 0x8718 -> IT8718 + 0x8726 -> IT8726 (datasheet wrongly says 0x8716) */ - printf("ITE? SuperIO found at 0x%02x: id=0x%04x, chipver=0x%01x\n", + printf("SuperI/O found at 0x%02x: id=0x%04x, chipver=0x%01x\n", port, id, chipver);
switch(id) { case 0x8702: case 0x8705: - case 0x8710: //pointless, IT8710 has different enable sequence case 0x8712: case 0x8716: case 0x8718: + case 0x8726: dump_ite(port, id); break; default: printf("no dump for id 0x%04x\n", id); break; } - // disable configuration + /* disable configuration */ regwrite(port, 0x02, 0x02); }
On Mon, Aug 27, 2007 at 01:41:54PM +0200, Carl-Daniel Hailfinger wrote:
This patch makes ITE SuperI/O probing/dumping a little bit more generic, fixes minor codingstyle issues and prepares the table for supporting more chips of the ITE IT87xx SuperI/O family.
Tested on my two ITE-powered boards as you requested.
With IT8702F-A:
No SuperI/O chip found at 0x002e No SuperIO chip found at 0x002e SuperI/O found at 0x2e: id=0x8702, chipver=0x3 ITE IT8702 No SuperI/O chip found at 0x004e No SuperIO chip found at 0x004e No SuperIO chip found at 0x004e
With IT8712F-A:
No SuperI/O chip found at 0x002e No SuperIO chip found at 0x002e SuperI/O found at 0x2e: id=0x8712, chipver=0x7 ITE IT8712 idx 07 20 21 22 23 24 2b val 09 87 12 07 01 00 00 def NA 87 12 08 00 00 00 switching to LDN 0x0 idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 switching to LDN 0x1 idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f switching to LDN 0x2 idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f switching to LDN 0x3 idx 30 60 61 62 63 70 74 f0 val 01 03 78 07 78 07 03 0b def 00 03 78 07 78 07 03 03 switching to LDN 0x4 idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 80 00 0a 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA switching to LDN 0x5 idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00 switching to LDN 0x6 idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 switching to LDN 0x7 idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 00 00 05 40 00 00 1f 00 00 08 00 00 00 00 00 00 00 04 00 00 01 00 00 00 00 00 01 00 00 00 00 00 05 40 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3f 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 30 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 switching to LDN 0x8 idx 30 60 61 70 f0 val 01 03 30 0a 00 def 00 03 00 0a 00 switching to LDN 0x9 idx 30 60 61 val 01 02 01 def 00 02 01 switching to LDN 0xa idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 No SuperI/O chip found at 0x004e No SuperIO chip found at 0x004e No SuperIO chip found at 0x004e
On 27.08.2007 22:08, Robert Millan wrote:
On Mon, Aug 27, 2007 at 01:41:54PM +0200, Carl-Daniel Hailfinger wrote:
This patch makes ITE SuperI/O probing/dumping a little bit more generic, fixes minor codingstyle issues and prepares the table for supporting more chips of the ITE IT87xx SuperI/O family.
Tested on my two ITE-powered boards as you requested.
Thanks!
With IT8702F-A:
No SuperI/O chip found at 0x002e No SuperIO chip found at 0x002e SuperI/O found at 0x2e: id=0x8702, chipver=0x3 ITE IT8702 No SuperI/O chip found at 0x004e No SuperIO chip found at 0x004e No SuperIO chip found at 0x004e
As expected.
With IT8712F-A:
No SuperI/O chip found at 0x002e No SuperIO chip found at 0x002e SuperI/O found at 0x2e: id=0x8712, chipver=0x7 ITE IT8712 idx 07 20 21 22 23 24 2b val 09 87 12 07 01 00 00 def NA 87 12 08 00 00 00 [...]
As expected.
What sort of problems did the board with the IT8712F have? With a dump from under proprietary bios and lb, we can compare and make sure the right registers are set the way you need them.
Regards, Carl-Daniel
On Tue, Aug 28, 2007 at 06:31:40PM +0200, Carl-Daniel Hailfinger wrote:
What sort of problems did the board with the IT8712F have?
- PS/2 keyboard doesn't work (neither in FILO or Linux). - USB keyboard works on Linux but not on FILO. - PCI (not PCI-e/AGP/whatever) VGA works fine, but if I plug an additional ethernet card (tried 3 different brands), VGA output is broken. The only thing I see in display is " Φ╘±╣↓" (always the same). - Serial port works fine, though.
With a dump from under proprietary bios and lb, we can compare and make sure the right registers are set the way you need them.
Attached.
TIA
On 29.08.2007 13:30, Robert Millan wrote:
On Tue, Aug 28, 2007 at 06:31:40PM +0200, Carl-Daniel Hailfinger wrote:
What sort of problems did the board with the IT8712F have?
- PS/2 keyboard doesn't work (neither in FILO or Linux).
- USB keyboard works on Linux but not on FILO.
- PCI (not PCI-e/AGP/whatever) VGA works fine, but if I plug an additional ethernet card (tried 3 different brands), VGA output is broken. The only thing I see in display is " Φ╘±╣↓" (always the same).
- Serial port works fine, though.
With a dump from under proprietary bios and lb, we can compare and make sure the right registers are set the way you need them.
SuperI/O found at 0x2e: id=0x8712, chipver=0x7 ITE IT8712 switching to LDN 0x4 idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 80 00 0a 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA
ldn 0x4, idx 0x70: interrupt level of environment controller. prop: 0x00, lb 0x09. change?
switching to LDN 0x5 idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00
ldn 0x5, idx 0xf0: keyboard special config. prop: 0x68, lb 0x40. prop: no irq sharing, lb: active irq sharing. change? prop: kbc clock 8mhz, lb: kbc clock 12mhz. FIX!
IF you fix the stuff mentioned above, PS/2 keyboard should work fine. PCI is not affected by SuperIO config. USB keyboard can be investigated later if the PS/2 fixes don't help.
Carl-Daniel
On Wed, Aug 29, 2007 at 06:35:23PM +0200, Carl-Daniel Hailfinger wrote:
SuperI/O found at 0x2e: id=0x8712, chipver=0x7 ITE IT8712 switching to LDN 0x4 idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 80 00 0a 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA
ldn 0x4, idx 0x70: interrupt level of environment controller. prop: 0x00, lb 0x09. change?
switching to LDN 0x5 idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00
ldn 0x5, idx 0xf0: keyboard special config. prop: 0x68, lb 0x40. prop: no irq sharing, lb: active irq sharing. change? prop: kbc clock 8mhz, lb: kbc clock 12mhz. FIX!
IF you fix the stuff mentioned above, PS/2 keyboard should work fine. PCI is not affected by SuperIO config. USB keyboard can be investigated later if the PS/2 fixes don't help.
Thanks for the hints. I changed the mentioned registers to the same values they had with propietary BIOS, but to no avail. Attaching a diff of my changes.
Any idea? Should I go after all the other disparities?
On Fri, Aug 31, 2007 at 07:38:25PM +0200, Robert Millan wrote:
Attaching a diff of my changes.
Really attaching it now ;-)
On 31.08.2007 19:38, Robert Millan wrote:
On Wed, Aug 29, 2007 at 06:35:23PM +0200, Carl-Daniel Hailfinger wrote:
SuperI/O found at 0x2e: id=0x8712, chipver=0x7 ITE IT8712 switching to LDN 0x4 idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 80 00 0a 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA
ldn 0x4, idx 0x70: interrupt level of environment controller. prop: 0x00, lb 0x09. change?
switching to LDN 0x5 idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00
ldn 0x5, idx 0xf0: keyboard special config. prop: 0x68, lb 0x40. prop: no irq sharing, lb: active irq sharing. change? prop: kbc clock 8mhz, lb: kbc clock 12mhz. FIX!
IF you fix the stuff mentioned above, PS/2 keyboard should work fine. PCI is not affected by SuperIO config. USB keyboard can be investigated later if the PS/2 fixes don't help.
Thanks for the hints. I changed the mentioned registers to the same values they had with propietary BIOS, but to no avail. Attaching a diff of my changes.
Any idea? Should I go after all the other disparities?
Only those which I listed in my earlier mail plus the following list:
--- propietary 2007-09-01 20:21:24.000000000 +0200 +++ lb 2007-09-01 20:21:24.000000000 +0200 switching to LDN 0x2 (serial port 2) idx 30 60 61 70 -val 00 00 00 00 +val 01 02 f8 03 prop disables com2 an clears baseaddr+irq. FIX.
switching to LDN 0x3 idx f0 -val 0b +val 03 fascinating. the board can output post codes via parallel port. maybe?
switching to LDN 0x4 idx 62 63 70 -val 00 00 00 +val 02 30 09 pme direct access addr + ec interrupt level FIX.
switching to LDN 0x5 idx f0 -val 68 +val 40 keyboard clock etc. FIX.
switching to LDN 0x7 idx 25 27 62 b2 ba c0 c2 c8 ca cb -val 00 05 08 01 01 00 05 00 05 00 +val 01 00 00 00 00 01 00 01 00 40 idx 25: pin 84 smart card present? maybe? idx 27: gpio 30+32. FIX. idx 62: simeple i/o base addr. FIX. idx b2: gpio pin set 3: gpio invert polarity. FIX. idx ba: gpio pin set 3: gpio pullup. FIX. idx c0: simple i/o set 1: enable. FIX. idx c2: simple i/o set 3: enable. FIX. idx c8: simple i/o set 1: input mode. FIX. idx ca: simple i/o set 3: input mode. FIX. idx cb: simple i/o set 4: input mode. FIX.
switching to LDN 0x8 idx 30 61 -val 01 30 +val 00 00 ok.
switching to LDN 0x9 idx 30 -val 01 +val 00 ok.
You patch in the other mail looked fine. Fix the issues mentioned above as "FIX" and post another probe_superio from a lb boot after fixes.
Regards, Carl-Daniel
On Sat, Sep 01, 2007 at 09:00:57PM +0200, Carl-Daniel Hailfinger wrote:
You patch in the other mail looked fine. Fix the issues mentioned above as "FIX" and post another probe_superio from a lb boot after fixes.
This is getting weird. I just added all the fixes, and got my superio layout to be as similar as the propietary one as shown below, but the PS/2 keyboard still won't work.
Any idea what else can be tried?
$ sudo ./superiotool -d | diff -u PROPIETARY_DUMP - --- PROPIETARY_DUMP 2007-09-25 23:40:14.000000000 +0200 +++ - 2007-09-26 00:21:11.266993669 +0200 @@ -1,7 +1,7 @@ Found ITE IT8712F (id=0x8712, rev=0x7) at port=0x2e Register dump: idx 07 20 21 22 23 24 2b -val 0a 87 12 07 01 00 00 +val 06 87 12 07 01 00 00 def NA 87 12 08 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 @@ -13,7 +13,7 @@ def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 -val 00 00 00 00 00 50 00 7f +val 01 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0
The first difference I don't know how to change, but strangely the next time I run the same command it isn't detected anymore. As for the second one, it still appears despite me setting that register explicitly like all the others, and commenting out the line in it8712f_early_serial.c that set it to 0x01 as well.
(note: afaict, this board has no com2 port. could this affect the superio?)
On 26.09.2007 00:25, Robert Millan wrote:
On Sat, Sep 01, 2007 at 09:00:57PM +0200, Carl-Daniel Hailfinger wrote:
You patch in the other mail looked fine. Fix the issues mentioned above as "FIX" and post another probe_superio from a lb boot after fixes.
This is getting weird. I just added all the fixes, and got my superio layout to be as similar as the propietary one as shown below, but the PS/2 keyboard still won't work.
Any idea what else can be tried?
$ sudo ./superiotool -d | diff -u PROPIETARY_DUMP - --- PROPIETARY_DUMP 2007-09-25 23:40:14.000000000 +0200 +++ - 2007-09-26 00:21:11.266993669 +0200 @@ -1,7 +1,7 @@ Found ITE IT8712F (id=0x8712, rev=0x7) at port=0x2e Register dump: idx 07 20 21 22 23 24 2b -val 0a 87 12 07 01 00 00 +val 06 87 12 07 01 00 00
That's expected. Basically, idx 07 is a selector for the subfunction you want to access next, so it will be in the state the last access left it.
def NA 87 12 08 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 @@ -13,7 +13,7 @@ def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 -val 00 00 00 00 00 50 00 7f +val 01 00 00 00 00 50 00 7f
Interesting...
def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0
The first difference I don't know how to change, but strangely the next time I run the same command it isn't detected anymore. As for the second one, it
See above.
still appears despite me setting that register explicitly like all the others, and commenting out the line in it8712f_early_serial.c that set it to 0x01 as well.
It would be interesting to dump LDN 0x02, idx 0x30 at various times during BIOS init.
(note: afaict, this board has no com2 port. could this affect the superio?)
Should not.
Please provide a diff between dmesg under LB and proprietary BIOS. I suspect some keyboard init is done differently.
Also note that some superio internal state will NOT be dumped by superiotool and your problem could very well be there. Unfortunately, we don't have a way to retrieve the internal state.
Carl-Daniel
On Thu, Sep 27, 2007 at 03:56:20PM +0200, Carl-Daniel Hailfinger wrote:
Please provide a diff between dmesg under LB and proprietary BIOS. I suspect some keyboard init is done differently.
Here.
On 28.09.2007 21:14, Robert Millan wrote:
On Thu, Sep 27, 2007 at 03:56:20PM +0200, Carl-Daniel Hailfinger wrote:
Please provide a diff between dmesg under LB and proprietary BIOS. I suspect some keyboard init is done differently.
Here.
There's quite some stuff broken. Comments below.
--- dmesg_lb 2007-09-28 21:13:12.000000000 +0200 +++ dmesg_bios 2007-09-28 21:13:12.000000000 +0200 @@ -1,50 +1,76 @@ Linux version 2.6.22-2-686 (Debian 2.6.22-4) (waldi@debian.org) (gcc version 4.1.3 20070812 (prerelease) (Debian 4.1.2-15)) #1 SMP Fri Aug 31 00:24:01 UTC 2007 BIOS-provided physical RAM map:
- BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
- BIOS-e820: 0000000000100000 - 0000000060000000 (usable)
-640MB HIGHMEM available.
- BIOS-e820: 0000000000000000 - 000000000009f800 (usable)
- BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved)
- BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
- BIOS-e820: 0000000000100000 - 000000005fff0000 (usable)
- BIOS-e820: 000000005fff0000 - 000000005fff3000 (ACPI NVS)
- BIOS-e820: 000000005fff3000 - 0000000060000000 (ACPI data)
- BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved)
- BIOS-e820: 00000000fec00000 - 0000000100000000 (reserved)
+639MB HIGHMEM available. 896MB LOWMEM available. -found SMP MP-table at 00000010 -Entering add_active_range(0, 0, 393216) 0 entries of 256 used +found SMP MP-table at 000f5650 +Entering add_active_range(0, 0, 393200) 0 entries of 256 used Zone PFN ranges: DMA 0 -> 4096 Normal 4096 -> 229376
- HighMem 229376 -> 393216
- HighMem 229376 -> 393200
early_node_map[1] active PFN ranges
- 0: 0 -> 393216
-On node 0 totalpages: 393216
- 0: 0 -> 393200
+On node 0 totalpages: 393200 DMA zone: 32 pages used for memmap DMA zone: 0 pages reserved DMA zone: 4064 pages, LIFO batch:0 Normal zone: 1760 pages used for memmap Normal zone: 223520 pages, LIFO batch:31
- HighMem zone: 1280 pages used for memmap
- HighMem zone: 162560 pages, LIFO batch:31
-DMI not present or invalid.
- HighMem zone: 1279 pages used for memmap
- HighMem zone: 162545 pages, LIFO batch:31
+DMI 2.3 present. +ACPI: RSDP 000F76C0, 0014 (r0 Nvidia) +ACPI: RSDT 5FFF3040, 0034 (r1 Nvidia AWRDACPI 42302E31 AWRD 0) +ACPI: FACP 5FFF30C0, 0074 (r1 Nvidia AWRDACPI 42302E31 AWRD 0) +ACPI: DSDT 5FFF3180, 6264 (r1 NVIDIA AWRDACPI 1000 MSFT 100000E) +ACPI: FACS 5FFF0000, 0040 +ACPI: SRAT 5FFF9500, 0090 (r1 AMD HAMMER 1 AMD 1) +ACPI: MCFG 5FFF9600, 003C (r1 Nvidia AWRDACPI 42302E31 AWRD 0) +ACPI: APIC 5FFF9440, 007C (r1 Nvidia AWRDACPI 42302E31 AWRD 0) Nvidia board detected. Ignoring ACPI timer override. If you got timer trouble try acpi_use_timer_override -Intel MultiProcessor Specification v1.4
- Virtual Wire compatibility mode.
-OEM ID: ASUS Product ID: A8NE APIC at: 0xFEE00000 +ACPI: PM-Timer IO Port: 0x4008 +ACPI: Local APIC address 0xfee00000 +ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) Processor #0 15:15 APIC version 16 -I/O APIC #1 Version 17 at 0xFC900000. +ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] disabled) +ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0]) +IOAPIC[0]: apic_id 2, version 17, address 0xfec00000, GSI 0-23 +ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) +ACPI: BIOS IRQ0 pin2 override ignored. +ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +ACPI: INT_SRC_OVR (bus 0 bus_irq 14 global_irq 14 high edge) +ACPI: INT_SRC_OVR (bus 0 bus_irq 15 global_irq 15 high edge) +ACPI: IRQ9 used by override. +ACPI: IRQ14 used by override. +ACPI: IRQ15 used by override. Enabling APIC mode: Flat. Using 1 I/O APICs -Processors: 1 -Allocating PCI resources starting at 70000000 (gap: 60000000:a0000000) -Built 1 zonelists. Total pages: 390144 -Kernel command line: root=/dev/hda3 ro +Using ACPI (MADT) for SMP configuration information +Allocating PCI resources starting at 68000000 (gap: 60000000:80000000) +Built 1 zonelists. Total pages: 390129 +Kernel command line: root=/dev/hda3 ro mapped APIC to ffffd000 (fee00000) -mapped IOAPIC to ffffc000 (fc900000) +mapped IOAPIC to ffffc000 (fec00000) Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 PID hash table entries: 4096 (order: 12, 16384 bytes) -Detected 2211.367 MHz processor. +Detected 2211.369 MHz processor. spurious 8259A interrupt: IRQ7. Console: colour VGA+ 80x25 Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) -Memory: 1550348k/1572864k available (1688k kernel code, 21364k reserved, 653k data, 244k init, 655360k highmem) +Memory: 1550220k/1572800k available (1688k kernel code, 21368k reserved, 653k data, 244k init, 655296k highmem) virtual kernel memory layout: fixmap : 0xfff4e000 - 0xfffff000 ( 708 kB) pkmap : 0xff800000 - 0xffc00000 (4096 kB) @@ -54,7 +80,7 @@ .data : 0xc02a62bf - 0xc03497e4 ( 653 kB) .text : 0xc0100000 - 0xc02a62bf (1688 kB) Checking if this processor honours the WP bit even in supervisor mode... Ok. -Calibrating delay using timer specific routine.. 4429.03 BogoMIPS (lpj=8858066) +Calibrating delay using timer specific routine.. 4425.47 BogoMIPS (lpj=8850948) Security Framework v1.0.0 initialized SELinux: Disabled at boot. Capability LSM initialized @@ -70,50 +96,86 @@ SMP alternatives: switching to UP code Freeing SMP alternatives: 11k freed ACPI: Core revision 20070126 -ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126] -ACPI: Unable to load the System Description Tables CPU0: AMD Athlon(tm) 64 Processor 3500+ stepping 02 -Total of 1 processors activated (4429.03 BogoMIPS). +Total of 1 processors activated (4425.47 BogoMIPS). ENABLING IO-APIC IRQs -..TIMER: vector=0x31 apic1=0 pin1=2 apic2=0 pin2=0 -..MP-BIOS bug: 8254 timer not connected to IO-APIC
Bad. Can we perform that work in LB?
-...trying to set up timer (IRQ0) through the 8259A ... -..... (found pin 0) ...works. +..TIMER: vector=0x31 apic1=0 pin1=0 apic2=-1 pin2=-1 Brought up 1 CPUs Booting paravirtualized kernel on bare hardware NET: Registered protocol family 16 -PCI: Using configuration type 1 +ACPI: bus type pci registered +PCI: Using MMCONFIG +PCI: No mmconfig possible on device 00:18 Setting up standard PCI resources -ACPI: Interpreter disabled. -Linux Plug and Play Support v0.97 (c) Adam Belay -pnp: PnP ACPI: disabled -PnPBIOS: Scanning system for PnP BIOS support... -PnPBIOS: PnP BIOS support was not detected. -PCI: Probing PCI hardware +ACPI: Interpreter enabled +ACPI: (supports S0 S1 S3 S4 S5) +ACPI: Using IOAPIC for interrupt routing +ACPI: PCI Root Bridge [PCI0] (0000:00) PCI: Probing PCI hardware (bus 00) PCI: Transparent bridge - 0000:00:09.0 -PCI: Unable to handle 64-bit address space for bridge 0000:00:0b.0 -PCI: Unable to handle 64-bit address space for bridge 0000:00:0c.0 -PCI: Unable to handle 64-bit address space for bridge 0000:00:0d.0 -PCI: Unable to handle 64-bit address space for bridge 0000:00:0e.0
This is not 64bit space, but a ranges going backwards. Not keyboard related.
-PCI: Using IRQ router default [10de/005c] at 0000:00:09.0 -PCI->APIC IRQ transform: 0000:00:01.1[A] -> IRQ 10 -PCI->APIC IRQ transform: 0000:00:02.0[A] -> IRQ 21 -PCI->APIC IRQ transform: 0000:00:02.1[B] -> IRQ 20 -PCI->APIC IRQ transform: 0000:00:07.0[A] -> IRQ 23 -PCI->APIC IRQ transform: 0000:00:08.0[A] -> IRQ 22 -PCI->APIC IRQ transform: 0000:00:0a.0[A] -> IRQ 23 -PCI BIOS passed nonexistent PCI bus 1!
Must fix, but also not keyboard related.
-PCI: Cannot allocate resource region 5 of device 0000:00:01.1 +ACPI: PCI Interrupt Routing Table [_SB_.PCI0._PRT] +ACPI: PCI Interrupt Routing Table [_SB_.PCI0.HUB0._PRT] +ACPI: PCI Interrupt Link [LNK1] (IRQs *3 4 5 7 9 10 11 12 14 15) +ACPI: PCI Interrupt Link [LNK2] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [LNK3] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [LNK4] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [LNK5] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [LUBA] (IRQs *3 4 5 7 9 10 11 12 14 15) +ACPI: PCI Interrupt Link [LUBB] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [LMAC] (IRQs 3 4 *5 7 9 10 11 12 14 15) +ACPI: PCI Interrupt Link [LACI] (IRQs 3 4 5 7 9 10 *11 12 14 15) +ACPI: PCI Interrupt Link [LMCI] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [LSMB] (IRQs 3 4 *5 7 9 10 11 12 14 15) +ACPI: PCI Interrupt Link [LUB2] (IRQs 3 4 5 7 9 10 *11 12 14 15) +ACPI: PCI Interrupt Link [LIDE] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [LSID] (IRQs 3 4 5 7 9 10 *11 12 14 15) +ACPI: PCI Interrupt Link [LFID] (IRQs 3 4 *5 7 9 10 11 12 14 15) +ACPI: PCI Interrupt Link [LPCA] (IRQs 3 4 5 7 9 10 11 12 14 15) *0, disabled. +ACPI: PCI Interrupt Link [APC1] (IRQs 16) *0 +ACPI: PCI Interrupt Link [APC2] (IRQs 17) *0, disabled. +ACPI: PCI Interrupt Link [APC3] (IRQs 18) *0, disabled. +ACPI: PCI Interrupt Link [APC4] (IRQs 19) *0, disabled. +ACPI: PCI Interrupt Link [APC5] (IRQs *16), disabled. +ACPI: PCI Interrupt Link [APCF] (IRQs 20 21 22 23) *0 +ACPI: PCI Interrupt Link [APCG] (IRQs 20 21 22 23) *0, disabled. +ACPI: PCI Interrupt Link [APCH] (IRQs 20 21 22 23) *0 +ACPI: PCI Interrupt Link [APCJ] (IRQs 20 21 22 23) *0 +ACPI: PCI Interrupt Link [APCK] (IRQs 20 21 22 23) *0, disabled. +ACPI: PCI Interrupt Link [APCS] (IRQs 20 21 22 23) *0 +ACPI: PCI Interrupt Link [APCL] (IRQs 20 21 22 23) *0 +ACPI: PCI Interrupt Link [APCZ] (IRQs 20 21 22 23) *0, disabled. +ACPI: PCI Interrupt Link [APSI] (IRQs 20 21 22 23) *0 +ACPI: PCI Interrupt Link [APSJ] (IRQs 20 21 22 23) *0 +ACPI: PCI Interrupt Link [APCP] (IRQs 20 21 22 23) *0, disabled. +Linux Plug and Play Support v0.97 (c) Adam Belay +pnp: PnP ACPI init +ACPI: bus type pnp registered +pnp: PnP ACPI: found 15 devices +ACPI: ACPI bus type pnp unregistered +PnPBIOS: Disabled by ACPI PNP +PCI: Using ACPI for IRQ routing +PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report NET: Registered protocol family 8 NET: Registered protocol family 20 +ACPI: RTC can wake from S4 +pnp: 00:01: ioport range 0x4000-0x407f has been reserved +pnp: 00:01: ioport range 0x4080-0x40ff has been reserved +pnp: 00:01: ioport range 0x4400-0x447f has been reserved +pnp: 00:01: ioport range 0x4480-0x44ff has been reserved +pnp: 00:01: ioport range 0x4800-0x487f has been reserved +pnp: 00:01: ioport range 0x4880-0x48ff has been reserved +pnp: 00:0d: iomem range 0xe0000000-0xefffffff could not be reserved +pnp: 00:0e: iomem range 0xf0000-0xf3fff could not be reserved +pnp: 00:0e: iomem range 0xf4000-0xf7fff could not be reserved +pnp: 00:0e: iomem range 0xf8000-0xfbfff could not be reserved +pnp: 00:0e: iomem range 0xfc000-0xfffff could not be reserved +Time: tsc clocksource has been installed. PCI: Bridge: 0000:00:09.0 IO window: disabled.
- MEM window: fc000000-fc8fffff
- PREFETCH window: 70000000-700fffff
- MEM window: d0000000-d1ffffff
- PREFETCH window: 68000000-680fffff
PCI: Bridge: 0000:00:0b.0 IO window: disabled. -Time: tsc clocksource has been installed. MEM window: disabled. PREFETCH window: disabled. PCI: Bridge: 0000:00:0c.0 @@ -142,7 +204,7 @@ checking if image is initramfs... it is Freeing initrd memory: 5286k freed audit: initializing netlink socket (disabled) -audit(1191006556.256:1): initialized +audit(1191006861.244:1): initialized highmem bounce pool size: 64 pages VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) @@ -151,121 +213,149 @@ io scheduler deadline registered io scheduler cfq registered (default) PCI: Found disabled HT MSI Mapping on 0000:00:0b.0 -PCI: Found disabled HT MSI Mapping on 0000:00:00.0 -PCI: MSI quirk detected. MSI disabled on chipset 0000:00:0b.0.
Why not enable HT MSI?
+PCI: Found enabled HT MSI Mapping on 0000:00:00.0 +PCI: Linking AER extended capability on 0000:00:0b.0 PCI: Found disabled HT MSI Mapping on 0000:00:0c.0 -PCI: Found disabled HT MSI Mapping on 0000:00:00.0 -PCI: MSI quirk detected. MSI disabled on chipset 0000:00:0c.0. +PCI: Found enabled HT MSI Mapping on 0000:00:00.0 +PCI: Linking AER extended capability on 0000:00:0c.0 PCI: Found disabled HT MSI Mapping on 0000:00:0d.0 -PCI: Found disabled HT MSI Mapping on 0000:00:00.0 -PCI: MSI quirk detected. MSI disabled on chipset 0000:00:0d.0. +PCI: Found enabled HT MSI Mapping on 0000:00:00.0 +PCI: Linking AER extended capability on 0000:00:0d.0 PCI: Found disabled HT MSI Mapping on 0000:00:0e.0 -PCI: Found disabled HT MSI Mapping on 0000:00:00.0 -PCI: MSI quirk detected. MSI disabled on chipset 0000:00:0e.0. -Boot video device is 0000:01:06.0
Look at the boot video device.
+PCI: Found enabled HT MSI Mapping on 0000:00:00.0 +PCI: Linking AER extended capability on 0000:00:0e.0 +Boot video device is 0000:05:06.0
The bus numbering difference can probably be explained.
PCI: Setting latency timer of device 0000:00:0b.0 to 64 assign_interrupt_mode Found MSI capability Allocate Port Service[0000:00:0b.0:pcie00] +Allocate Port Service[0000:00:0b.0:pcie03] PCI: Setting latency timer of device 0000:00:0c.0 to 64 assign_interrupt_mode Found MSI capability Allocate Port Service[0000:00:0c.0:pcie00] +Allocate Port Service[0000:00:0c.0:pcie03] PCI: Setting latency timer of device 0000:00:0d.0 to 64 assign_interrupt_mode Found MSI capability Allocate Port Service[0000:00:0d.0:pcie00] +Allocate Port Service[0000:00:0d.0:pcie03] PCI: Setting latency timer of device 0000:00:0e.0 to 64 assign_interrupt_mode Found MSI capability Allocate Port Service[0000:00:0e.0:pcie00] +Allocate Port Service[0000:00:0e.0:pcie03] isapnp: Scanning for PnP cards... +Switched to high resolution mode on CPU 0 isapnp: No Plug & Play device found Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A +00:08: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize -PNP: No PS/2 controller found. Probing ports directly. -i8042.c: Can't read CTR while initializing i8042. -i8042: probe of i8042 failed with error -5
Now that one is really really bad. You could try to make sure port 0x60,0x64 irq 1 are used as default ports in probing.
+PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1 +PNP: PS/2 controller doesn't have AUX irq; using default 12 +serio: i8042 KBD port at 0x60,0x64 irq 1 +serio: i8042 AUX port at 0x60,0x64 irq 12 mice: PS/2 mouse device common for all mice TCP bic registered NET: Registered protocol family 1 NET: Registered protocol family 17 Using IPI No-Shortcut mode Freeing unused kernel memory: 244k freed -thermal: Unknown symbol acpi_processor_set_thermal_limit -Clocksource tsc unstable (delta = 504074564 ns) -Time: pit clocksource has been installed.
And that's the missing PM timer.
/proc/interrups /proc/ioports /proc/iomem would also be useful to compare.
Carl-Daniel
On Fri, Sep 28, 2007 at 10:41:00PM +0200, Carl-Daniel Hailfinger wrote:
/proc/interrups /proc/ioports /proc/iomem would also be useful to compare.
Here.
On Mon, Aug 27, 2007 at 01:41:54PM +0200, Carl-Daniel Hailfinger wrote:
This patch makes ITE SuperI/O probing/dumping a little bit more generic, fixes minor codingstyle issues and prepares the table for supporting more chips of the ITE IT87xx SuperI/O family.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Thanks, r2750.
I'll fixup a few more cosmetics in an extra commit.
Uwe.
-
Carl-Daniel Hailfinger -
Robert Millan -
Uwe Hermann