[commit] r5917 - in trunk/src: cpu/intel/slot_1 mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/asus/p2b mainboard/asus/p2b-d mainboard/asus/p2b-ds mainbo...
Author: uwe Date: Wed Oct 6 21:32:39 2010 New Revision: 5917 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5917
Log: Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.
- Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
- Remove "select ROMCC" from all 440BX board Kconfig files.
- Drop all early_mtrr_init() calls, that's done by CAR code now.
Various small fixes were needed to make it build:
- Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways.
- Remove the "static" from the main() functions in romstage.c files.
- Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig.
- Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards.
- Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files.
Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Patrick Georgi patrick@georgi-clan.de
Modified: trunk/src/cpu/intel/slot_1/Kconfig trunk/src/cpu/intel/slot_1/Makefile.inc trunk/src/mainboard/a-trend/atc-6220/Kconfig trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/Kconfig trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/asus/p2b-d/Kconfig trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/Kconfig trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/Kconfig trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/Kconfig trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/Kconfig trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/Kconfig trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/azza/pt-6ibd/Kconfig trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/biostar/m6tba/Kconfig trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c trunk/src/mainboard/msi/ms6119/Kconfig trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/Kconfig trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/Kconfig trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/nokia/ip530/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/tyan/s1846/Kconfig trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/northbridge/intel/i440bx/debug.c trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h
Modified: trunk/src/cpu/intel/slot_1/Kconfig ============================================================================== --- trunk/src/cpu/intel/slot_1/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/cpu/intel/slot_1/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -19,6 +19,7 @@
config CPU_INTEL_SLOT_1 bool + select CACHE_AS_RAM
config DCACHE_RAM_BASE hex
Modified: trunk/src/cpu/intel/slot_1/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/slot_1/Makefile.inc Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/cpu/intel/slot_1/Makefile.inc Wed Oct 6 21:32:39 2010 (r5917) @@ -27,3 +27,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc +
Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6220/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/a-trend/atc-6240/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6240/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: It's a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
/* FIXME: It's a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: It's a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/asus/p2b-d/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-d/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-d/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP
Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -27,16 +27,15 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -48,12 +47,9 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) { - early_mtrr_init(); - enable_lapic(); /* FIXME? */ - } + enable_lapic(); /* FIXME? */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ds/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP
Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -27,16 +27,15 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -48,12 +47,9 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) { - early_mtrr_init(); - enable_lapic(); /* FIXME? */ - } + enable_lapic(); /* FIXME? */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/asus/p2b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-f/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-f/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/asus/p2b-ls/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ls/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -48,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -63,10 +59,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/asus/p2b/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/asus/p3b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p3b-f/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p3b-f/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "southbridge/intel/i82371eb/i82371eb_early_pm.c" @@ -34,10 +33,10 @@ #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -81,11 +80,8 @@ outb(0x67, PM_IO_BASE + 0x37); }
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -100,12 +96,10 @@
enable_spd();
- /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */
disable_spd(); } -
Modified: trunk/src/mainboard/azza/pt-6ibd/Kconfig ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/azza/pt-6ibd/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: It's a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
/* FIXME: It's a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: It's a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/biostar/m6tba/Kconfig ============================================================================== --- trunk/src/mainboard/biostar/m6tba/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/biostar/m6tba/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ /* Enable access to the full ROM chip, needed very early by CBFS. */ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
- /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -26,7 +26,6 @@ select SOUTHBRIDGE_INTEL_I82371EB # should be SUPERIO_NSC_PC97307! select SUPERIO_NSC_PC97317 - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #include "superio/nsc/pc97317/pc97317_early_serial.c" +#include <lib.h>
/* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #define SERIAL_DEV PNP_DEV(0x15c, PC97317_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: Should be PC97307! */ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +void it8671f_48mhz_clkin(void); #include "superio/ite/it8671f/it8671f_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
@@ -47,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +58,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -26,7 +26,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +static void it8671f_48mhz_clkin(void); #include "superio/ite/it8671f/it8671f_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
@@ -47,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - it8671f_48mhz_clkin(); it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -62,9 +59,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ }
Modified: trunk/src/mainboard/msi/ms6119/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6119/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6119/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6119/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/msi/ms6147/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6147/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6147/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6147/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/x86/bist.h> #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -45,13 +44,10 @@ }
#include "northbridge/intel/i440bx/raminit.c" -/* #include "northbridge/intel/i440bx/debug.c" */ +#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,17 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); -#if 0 - ram_check(0, 640 * 1024); /* DOS-area */ - ram_check(0x00100000, 0x00400000); /* 1MB to 4MB */ - ram_check(0x00100000, 0x03ffffff); /* 1MB to 64MB- */ - ram_check(0x03fff000, 0x04000010); /* Across 64MB boundary */ - ram_check(0x07ffff00, 0x07fffff0); /* Just below 128MB */ - ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */ -#endif } -
Modified: trunk/src/mainboard/msi/ms6156/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6156/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6156/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6156/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/nokia/ip530/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,9 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ }
Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +void it8671f_48mhz_clkin(void); #include "superio/ite/it8671f/it8671f_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
@@ -47,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +58,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/tyan/s1846/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s1846/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/tyan/s1846/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_NSC_PC87309 - select ROMCC select UDELAY_TSC select BOARD_ROMSIZE_KB_256
Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/tyan/s1846/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87309/pc87309_early_serial.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
@@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/northbridge/intel/i440bx/debug.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/debug.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/northbridge/intel/i440bx/debug.c Wed Oct 6 21:32:39 2010 (r5917) @@ -1,6 +1,6 @@ - static void dump_spd_registers(void) { +#if CONFIG_DEBUG_RAM_SETUP int i; print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { @@ -32,6 +32,7 @@ print_debug("\n"); } } +#endif }
#if 0
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Wed Oct 6 21:32:39 2010 (r5917) @@ -63,95 +63,6 @@ return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; }
-static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned global_status_register; - unsigned byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHST_CMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* set the data word...*/ - outw(0, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHST_DAT) & 0xff; - - // Check for any result other than a command completion - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} - -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned value) -{ - unsigned global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHST_CMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* set the data word...*/ - outw(value, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - return 0; -} - - static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { unsigned status_register; @@ -199,41 +110,3 @@ return byte; }
-static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - unsigned global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR); - outb(address & 0xFF, smbus_io_base + SMBHST_CMD); - /* set up for a byte data write */ /* FIXME */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x2), smbus_io_base + SMBHST_CTL); - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* write the data word...*/ - outw(val, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) { - return SMBUS_ERROR; - } - return 0; -} -
-
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