Hi, I have read the excellent paper on FreeVGA http://www.linuxbios.org/data/vgabios/
and I am thinking on using it on a powerpc design we have made based on IBM 970fx ppc64 CPU (after it runs linuxbios of course, but I am trying to plan ahead and see what is needed to have PCI graphic cards running on it). I have looked at the x86emu code, and more precisely to the X86EMU_pioFuncs function which is in charge of I/O accesses whenever the VGA BIOS makes an x86 int/out instruction to some I/O port (for example to the range of VGA control registers in the 0x3XX region). The graphic I intend to use is an ATI Radeon RV100 PCI card. So it looks like I will have to program the X86EMU_pioFuncs with a function that will redirect I/O accesses from the low 0x3XX addresses, to the ATI PCI I/O region that contains VGA registers. Here is an excerpt of an "lspci -vv" on my graphic card (see below). I am planning to re-direct all these I/O accesses to the region 1 (I/O ports at f4015000). The VGA registers have to be in there...where else? So it shouldn't be too hard. Am I overlooking things? The FreeVGA paper said he should be rather complicated to do on powerpc....so i may be to optimistic
02:01.0 VGA compatible controller: ATI Technologies Inc Radeon RV100 QY [Radeon) Subsystem: ATI Technologies Inc: Unknown device 013b Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Ste- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbor- Latency: 255 (2000ns min) Interrupt: pin A routed to IRQ 30 Region 0: Memory at 0000000080000000 (32-bit, prefetchable) Region 1: I/O ports at f4015000 [size=256] Region 2: Memory at 00000000a0000000 (32-bit, non-prefetchable) [size=6] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3ho) Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Thanks a lot -jf simon
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On Tue, 2006-09-05 at 12:46 +0200, jf simon wrote:
Hi, I have read the excellent paper on FreeVGA http://www.linuxbios.org/data/vgabios/
and I am thinking on using it on a powerpc design we have made based on IBM 970fx ppc64 CPU (after it runs linuxbios of course, but I am trying to plan ahead and see what is needed to have PCI graphic cards running on it). I have looked at the x86emu code, and more precisely to the X86EMU_pioFuncs function which is in charge of I/O accesses whenever the VGA BIOS makes an x86 int/out instruction to some I/O port (for example to the range of VGA control registers in the 0x3XX region). The graphic I intend to use is an ATI Radeon RV100 PCI card. So it looks like I will have to program the X86EMU_pioFuncs with a function that will redirect I/O accesses from the low 0x3XX addresses, to the ATI PCI I/O region that contains VGA registers. Here is an excerpt of an "lspci -vv" on my graphic card (see below). I am planning to re-direct all these I/O accesses to the region 1 (I/O ports at f4015000). The VGA registers have to be in there...where else? So it shouldn't be too hard. Am I overlooking things? The FreeVGA paper said he should be rather complicated to do on powerpc....so i may be to optimistic
Those legacy IO ports are NOT necessary mapped to the PCI IO address. Some VGA card does and some others come with some kind of remapping or offset. Your system chipset should have a way to map legacy VGA IO ports to memory address. You have to read the doc to the PPC chipset carefully to find it out.
Ollie
Those legacy IO ports are NOT necessary mapped to the PCI IO address. Some VGA card does and some others come with some kind of remapping or offset. Your system chipset should have a way to map legacy VGA IO ports to memory address. You have to read the doc to the PPC chipset carefully to find it out.
I have read the chipset doc and there is no such VGA support. But could you plse explain more on the different ways for VGA cards to map the VGA registers? Since the registers are located on a PCI agent (the graphic card), there must be a way to access them by generating PCI cycles? Thanks -jf simon
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On Tue, 2006-09-05 at 20:02 +0200, jean-francois simon wrote:
Those legacy IO ports are NOT necessary mapped to the PCI IO address. Some VGA card does and some others come with some kind of remapping or offset. Your system chipset should have a way to map legacy VGA IO ports to memory address. You have to read the doc to the PPC chipset carefully to find it out.I have read the chipset doc and there is no such VGA support. But could you plse explain more on the different ways for VGA cards to map the VGA registers? Since the registers are located on a PCI agent (the graphic card), there must be a way to access them by generating PCI cycles? Thanks
I don't know how exactly those legacy IO address is implemented by the HW and/or the bus protocol. But the Appendix G of PCI sepc says it is possible for PCI device to decode those legacy ports independent of the base address register.
Ollie
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jean-francois simon -
jf simon
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ollie