Attached please find a patch which adds support for the Bcom P680 mainboard. This board is a thin client system, used in (at least) the Neoware e140 thin client. It's essentially the same as the epia-cn, but with a Winbond W83697HG Super-IO.
Signed-off-by: Alex Mauer hawke@hawkesnest.net
This patch is based on an svn cp of the jetway j7f24 target/mainboard, so it doesn't show the entire add for those files.
sweet. Acked-by: Ronald G. Minnich rminnich@gmail.com
but let's see if there are other comments.
ron
On Tue, Oct 14, 2008 at 1:27 PM, Alex Mauer hawke@hawkesnest.net wrote:
Attached please find a patch which adds support for the Bcom P680 mainboard. This board is a thin client system, used in (at least) the Neoware e140 thin client. It's essentially the same as the epia-cn, but with a Winbond W83697HG Super-IO.
Signed-off-by: Alex Mauer hawke@hawkesnest.net
This patch is based on an svn cp of the jetway j7f24 target/mainboard, so it doesn't show the entire add for those files.
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On Tue, Oct 14, 2008 at 7:41 PM, ron minnich rminnich@gmail.com wrote:
sweet. Acked-by: Ronald G. Minnich rminnich@gmail.com
but let's see if there are other comments.
I've got no problems with it, even the coding style looks clean to me.
Acked-by: Corey Osgood corey.osgood@gmail.com
-Corey
ron
On Tue, Oct 14, 2008 at 1:27 PM, Alex Mauer hawke@hawkesnest.net wrote:
Attached please find a patch which adds support for the Bcom P680
mainboard.
This board is a thin client system, used in (at least) the Neoware e140 thin client. It's essentially the same as the epia-cn, but with a
Winbond
W83697HG Super-IO.
Signed-off-by: Alex Mauer hawke@hawkesnest.net
This patch is based on an svn cp of the jetway j7f24 target/mainboard, so
it
doesn't show the entire add for those files.
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On Tue, Oct 14, 2008 at 03:27:04PM -0500, Alex Mauer wrote:
Index: src/mainboard/bcom/winnetp680/Config.lb
--- src/mainboard/bcom/winnetp680/Config.lb (revision 3654) +++ src/mainboard/bcom/winnetp680/Config.lb (working copy) @@ -99,16 +99,14 @@ register "ide1_80pin_cable" = "0" register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d"
device pci a.0 on end # Firewire
device pci f.0 on end # SATA
device pci f.1 on end # IDE
device pci 10.0 on end # OHCI
device pci 10.1 on end # OHCI
device pci 10.2 on end # OHCI
device pci 10.3 on end # OHCI
device pci f.0 on end # IDE
device pci 10.0 on end # UHCI
device pci 10.1 on end # UHCI
device pci 10.2 on end # UHCI
device pci 10.3 on end # UHCI device pci 10.4 on end # EHCI device pci 11.0 on # Southbridge LPC
chip superio/fintek/f71805f # Super I/O
chip superio/winbond/w83697hf # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6
At least the Super I/O parts are incorrect for the w83697hf, I talked with Alex on IRC about this, he'll post an updated patch today.
Uwe.
Uwe Hermann wrote:
At least the Super I/O parts are incorrect for the w83697hf, I talked with Alex on IRC about this, he'll post an updated patch today.
The logical devices which are present are actually correct, but there are some missing.
Attached is the updated patch. In addition to the previous changes (adding support for the BCom WinNET P680 board, and adding a function to change the 24/48Mhz clock input selector on the Winbond W83697 superio.)
This patch gives the board a correct IRQ table (from getpir -- the factory irq table was actually correct, it seems), and adds the superio logical devices to the mainboard's config.lb (all added devices are disabled, since they're not really present on the board.)
Signed-off-by: Alex Mauer hawke@hawkesnest.net
Index: src/superio/winbond/w83697hf/w83697hf_early_serial.c =================================================================== --- src/superio/winbond/w83697hf/w83697hf_early_serial.c (revision 3654) +++ src/superio/winbond/w83697hf/w83697hf_early_serial.c (working copy) @@ -35,6 +35,16 @@ outb(0xaa, port); }
+static void w83697hf_set_clksel_48(device_t dev) +{ + u16 port = dev >> 8; + pnp_enter_ext_func_mode(dev); + outb(0x24, port); + /* Set the clock input to 48Mhz */ + outb(inb(port+1)|0x40, port+1); + pnp_exit_ext_func_mode(dev); +} + static void w83697hf_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev);
Property changes on: src/mainboard/bcom/winnetp680 ___________________________________________________________________ Added: svn:mergeinfo
Index: src/mainboard/bcom/winnetp680/Config.lb =================================================================== --- src/mainboard/bcom/winnetp680/Config.lb (revision 3654) +++ src/mainboard/bcom/winnetp680/Config.lb (working copy) @@ -99,16 +99,14 @@ register "ide1_80pin_cable" = "0" register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d" - device pci a.0 on end # Firewire - device pci f.0 on end # SATA - device pci f.1 on end # IDE - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI + device pci f.0 on end # IDE + device pci 10.0 on end # UHCI + device pci 10.1 on end # UHCI + device pci 10.2 on end # UHCI + device pci 10.3 on end # UHCI device pci 10.4 on end # EHCI device pci 11.0 on # Southbridge LPC - chip superio/fintek/f71805f # Super I/O + chip superio/winbond/w83697hf # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -127,13 +125,17 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end + device pnp e2.6 off end # Consumer IR + device pnp e2.7 off end # Game port, GPIO 1 + device pnp e2.8 off end # MIDI port, GPIO 5 + device pnp e2.9 off end # GPIO 2-4 + device pnp e2.a off end # ACPI device pnp 2e.b on # HWM io 0x60 = 0xec00 end end end device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem device pci 12.0 on end # Ethernet end end Index: src/mainboard/bcom/winnetp680/irq_tables.c =================================================================== --- src/mainboard/bcom/winnetp680/irq_tables.c (revision 3654) +++ src/mainboard/bcom/winnetp680/irq_tables.c (working copy) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe aaron.lwe@gmail.com for VIA) + * Generated by GetPIR * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,24 +22,24 @@ #include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0x828, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Crap (miniport) */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*IRQ_SLOT_COUNT, /* There can be total 8 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0xc20, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x596, /* Device */ + 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x3e, /* Checksum */ + 0x73, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, Index: src/mainboard/bcom/winnetp680/Options.lb =================================================================== --- src/mainboard/bcom/winnetp680/Options.lb (revision 3654) +++ src/mainboard/bcom/winnetp680/Options.lb (working copy) @@ -63,7 +63,6 @@ uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD uses CONFIG_CHIP_NAME uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC @@ -81,7 +80,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default HAVE_HARD_RESET = 0 default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 +default IRQ_SLOT_COUNT = 8 default HAVE_ACPI_TABLES = 0 default HAVE_OPTION_TABLE = 1 default ROM_IMAGE_SIZE = 64 * 1024 Index: src/mainboard/bcom/winnetp680/auto.c =================================================================== --- src/mainboard/bcom/winnetp680/auto.c (revision 3654) +++ src/mainboard/bcom/winnetp680/auto.c (working copy) @@ -38,7 +38,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" -#include "southbridge/via/vt8235/vt8235_early_serial.c" +#include "superio/winbond/w83697hf/w83697hf_early_serial.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
static void memreset_setup(void) { @@ -96,7 +97,9 @@ /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
- enable_vt8235_serial(); + w83697hf_set_clksel_48(SERIAL_DEV); + + w83697hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init();
Index: src/mainboard/bcom/winnetp680/chip.h =================================================================== --- src/mainboard/bcom/winnetp680/chip.h (revision 3654) +++ src/mainboard/bcom/winnetp680/chip.h (working copy) @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-extern struct chip_operations mainboard_jetway_j7f24_ops; +extern struct chip_operations mainboard_bcom_winnetp680_ops;
-struct mainboard_jetway_j7f24_config { +struct mainboard_bcom_winnetp680_config { int nothing; }; Index: src/mainboard/bcom/winnetp680/mainboard.c =================================================================== --- src/mainboard/bcom/winnetp680/mainboard.c (revision 3654) +++ src/mainboard/bcom/winnetp680/mainboard.c (working copy) @@ -22,6 +22,6 @@ #include <device/device.h> #include "chip.h"
-struct chip_operations mainboard_jetway_j7f24_ops = { - CHIP_NAME("Jetway J7F[24]* Mainboard") +struct chip_operations mainboard_bcom_winnetp680_ops = { + CHIP_NAME("BCOM WinNET P680 Mainboard") }; Index: targets/bcom/winnetp680/Config.lb =================================================================== --- targets/bcom/winnetp680/Config.lb (revision 0) +++ targets/bcom/winnetp680/Config.lb (working copy) @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-target jetway-j7f24 -mainboard jetway/j7f24 +target bcom-winnet-p680 +mainboard bcom/winnetp680
option MAXIMUM_CONSOLE_LOGLEVEL=8 option DEFAULT_CONSOLE_LOGLEVEL=8 @@ -38,7 +38,7 @@ option ROM_SIZE = (512 * 1024)
romimage "image" - option COREBOOT_EXTRA_VERSION = "-j7f24" + option COREBOOT_EXTRA_VERSION = "-winnetp680" payload ../payload.elf end
Property changes on: targets/bcom/winnetp680/Config.lb ___________________________________________________________________ Added: svn:mergeinfo
On Wed, Oct 15, 2008 at 01:11:54PM -0500, Alex Mauer wrote:
Signed-off-by: Alex Mauer hawke@hawkesnest.net
With the changes below this is: Acked-by: Uwe Hermann uwe@hermann-uwe.de
Index: src/mainboard/bcom/winnetp680/Config.lb
--- src/mainboard/bcom/winnetp680/Config.lb (revision 3654) +++ src/mainboard/bcom/winnetp680/Config.lb (working copy) @@ -99,16 +99,14 @@ register "ide1_80pin_cable" = "0" register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d"
device pci a.0 on end # Firewire
device pci f.0 on end # SATA
device pci f.1 on end # IDE
device pci 10.0 on end # OHCI
device pci 10.1 on end # OHCI
device pci 10.2 on end # OHCI
device pci 10.3 on end # OHCI
device pci f.0 on end # IDE
device pci 10.0 on end # UHCI
device pci 10.1 on end # UHCI
device pci 10.2 on end # UHCI
device pci 10.3 on end # UHCI device pci 10.4 on end # EHCI device pci 11.0 on # Southbridge LPC
chip superio/fintek/f71805f # Super I/O
chip superio/winbond/w83697hf # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6
@@ -127,13 +125,17 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end
device pnp e2.6 off end # Consumer IR
e2 should be 2e, also in the lines below....
device pnp e2.7 off end # Game port, GPIO 1
device pnp e2.8 off end # MIDI port, GPIO 5
device pnp e2.9 off end # GPIO 2-4
device pnp e2.a off end # ACPI
device pnp 2e.b on # HWM io 0x60 = 0xec00
Why 0xec00 here? IIRC superiotool said 0x290 (which is the usual value for a hardware monitor).
end end end device pci 11.5 on end # AC'97 audio
end end# device pci 11.6 off end # AC'97 Modem device pci 12.0 on end # Ethernet
Index: src/mainboard/bcom/winnetp680/irq_tables.c
--- src/mainboard/bcom/winnetp680/irq_tables.c (revision 3654) +++ src/mainboard/bcom/winnetp680/irq_tables.c (working copy) @@ -2,7 +2,7 @@
- This file is part of the coreboot project.
- Copyright (C) 2008 VIA Technologies, Inc.
- (Written by Aaron Lwe aaron.lwe@gmail.com for VIA)
- Generated by GetPIR
(C) 2008 Alex Mauer hawke@hawkesnest.net
I'd say, but it doesn't really matter much.
Uwe.