Holding the s2895 in reset powers off the machine

[Myles Watson]

I have two boards, the s2892 and the s2895.  I can power on the s2892 while
holding in reset, but the s2895 powers off after a second.

Any guesses where I'd look for the solution?  SuperIO or Southbridge?

The factory BIOS has the same behavior.

Thanks,
Myles

[Harald Gutmann]

On Tuesday 07 July 2009 22:45:08 Myles Watson wrote:
> I have two boards, the s2892 and the s2895.  I can power on the s2892 while
> holding in reset, but the s2895 powers off after a second.

Just for my interest, but why does someone need to power on a system while 
holding the reset button?
> Any guesses where I'd look for the solution?  SuperIO or Southbridge?
>
> The factory BIOS has the same behavior.
>
> Thanks,
> Myles

Regards,
Harald

[Myles Watson]

> Just for my interest, but why does someone need to power on a system while
> holding the reset button?

In this case it is to allow my FPGA time to initialize (or for me to
reprogram it) before the Opteron tries to set up HyperTransport
communication with it.

I haven't spent much time thinking about other use cases.

Thanks,
Myles

[Peter Stuge]

Myles Watson wrote:
> > Just for my interest, but why does someone need to power on a
> > system while holding the reset button?
>
> In this case it is to allow my FPGA time to initialize (or for me
> to reprogram it) before the Opteron tries to set up HyperTransport
> communication with it.

For an ugly hack<tm> maybe it would work to pulse the reset.

Do the two boards have the same chipset?

//Peter

[Myles Watson]

On Tue, Jul 7, 2009 at 4:46 PM, Peter Stuge  wrote:
> Myles Watson wrote:
> > > Just for my interest, but why does someone need to power on a
> > > system while holding the reset button?
> >
> > In this case it is to allow my FPGA time to initialize (or for me
> > to reprogram it) before the Opteron tries to set up HyperTransport
> > communication with it.
>
> For an ugly hack<tm> maybe it would work to pulse the reset.

Maybe.  I'd have to use a signal generator, though.  HyperTransport
initialization is pretty fast.
> Do the two boards have the same chipset?

Yes, they're both nvidia ck804 + amd 8131.  They have different superIOs,
though.  The soft_reset and hard_reset code is in the ck804 code.

Thanks,
Myles

[Peter Stuge]

Myles Watson wrote:
> > Do the two boards have the same chipset?
>
> Yes, they're both nvidia ck804 + amd 8131.  They have different
> superIOs, though.  The soft_reset and hard_reset code is in the
> ck804 code.

Hm. It seems like this would be a hardware thing. Could the superio
have some kind of watchdog? Is it involved in power at all on the
2895?

//Peter

[Carl-Daniel Hailfinger]

On 07.07.2009 23:03, Myles Watson wrote:
> > Just for my interest, but why does someone need to power on a system while
> > holding the reset button?
>
> In this case it is to allow my FPGA time to initialize (or for me to
> reprogram it) before the Opteron tries to set up HyperTransport
> communication with it.

I have no idea if the reset button directly triggers a reset line or
something similar on the processor, but it would be interesting to know:
1. Does the power off also happen if you hold reset after the machine
has already been booted? (Do n seconds of reset always trigger a poweroff?)
2. Which part of the board reacts to the held reset line and triggers
the poweroff?
3. Is reset maybe somehow coupled to PWRGOOD and holding down reset is
perceived as electrical problem of the power supply?

Regards,
Carl-Daniel

[Peter Stuge]

Carl-Daniel Hailfinger wrote:
> Is reset maybe somehow coupled to PWRGOOD and holding down reset
>
> is perceived as electrical problem of the power supply?

I would be surprised.

The big question is indeed what is monitoring reset.

//Peter

[Rudolf Marek]

Hi,

Please tell what superios are there. The pwrgood is sometimes involved. It looks 
like a SIO thingie.

Rudolf

[Myles Watson]

On Wed, Jul 8, 2009 at 1:13 AM, Rudolf Marek  wrote:
> Hi,
>
> Please tell what superios are there. The pwrgood is sometimes involved. It
> looks like a SIO thingie.

smsc lpc47b397.

On Tue, Jul 7, 2009 at 6:17 PM, Carl-Daniel Hailfinger <
[e-mail]> wrote:
> I have no idea if the reset button directly triggers a reset line or
> something similar on the processor, but it would be interesting to know:
> Does the power off also happen if you hold reset after the machine
>
> has already been booted? (Do n seconds of reset always trigger a poweroff?)

No.  After a few seconds of booting you can hold it in reset as long as you
want.  Since there is no output (no post codes either), I haven't been able
to narrow it down.

What I'm hoping is that it is some setting that can be saved by the device
for the next boot.  Otherwise I have to figure out a workaround, since I
can't access the SuperIO before HT is initialized, and I need to hold the
board in reset before HT is initialized.
> Which part of the board reacts to the held reset line and triggers
>
> the poweroff?

I don't know.
> Is reset maybe somehow coupled to PWRGOOD and holding down reset is
>
> perceived as electrical problem of the power supply?

Since #1 is no, I don't think so.

Thanks,
Myles