[PATCH] flashrom: add SST49LF020 support

[Sven Schnelle]

Hi List,

i've added support for the SST 49LF020 Flash chip to flashrom. Basically
only the device Id differs, the programming algorithm seems to be the
same as for SST 49LF020A.

I've only tested read so far, i'm a bit reluctant to test
erase/programming without a backup BIOS chip :)

Index: flash.h
===================================================================
--- flash.h	(revision 3845)
+++ flash.h	(working copy)
@@ -356,6 +356,7 @@
 #define SST_39VF040		0xD7
 #define SST_49LF040B		0x50
 #define SST_49LF040		0x51
+#define SST_49LF020            0x61
 #define SST_49LF020A		0x52
 #define SST_49LF080A		0x5B
 #define SST_49LF002A		0x57
Index: flashchips.c
===================================================================
--- flashchips.c	(revision 3845)
+++ flashchips.c	(working copy)
@@ -626,6 +626,12 @@
     probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
    },

+	{"SST", "SST49LF020", SST_ID, SST_49LF020,
+	 256, 16 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_49lf040, write_49lf040
+	},
+
    {"SST", "SST49LF020A", SST_ID, SST_49LF020A,
     256, 16 * 1024,
     TEST_UNTESTED,

[Uwe Hermann]

On Sun, Jan 04, 2009 at 08:11:57PM +0100, Sven Schnelle wrote:
> Hi List,
>
> i've added support for the SST 49LF020 Flash chip to flashrom. Basically
> only the device Id differs, the programming algorithm seems to be the
> same as for SST 49LF020A.
>
> I've only tested read so far, i'm a bit reluctant to test
> erase/programming without a backup BIOS chip :)

You forgot the Signed-off-by for this patch, please repost with that.
> Index: flash.h
>
> --- flash.h	(revision 3845)
> +++ flash.h	(working copy)
> @@ -356,6 +356,7 @@
>  #define SST_39VF040		0xD7
>  #define SST_49LF040B		0x50
>  #define SST_49LF040		0x51
> +#define SST_49LF020            0x61
>  #define SST_49LF020A		0x52
>  #define SST_49LF080A		0x5B
>  #define SST_49LF002A		0x57
> Index: flashchips.c
> ===================================================================
> --- flashchips.c	(revision 3845)
> +++ flashchips.c	(working copy)
> @@ -626,6 +626,12 @@
>     probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
>    },
> {"SST", "SST49LF020", SST_ID, SST_49LF020,
> 256, 16 * 1024,
> TEST_UNTESTED,

As reading works, this is not UNSTESTED. At least PROBE and READ
should be marked as working.

Uwe.

[Sven Schnelle]

Uwe Hermann  writes:
> > i've added support for the SST 49LF020 Flash chip to flashrom. Basically
> > only the device Id differs, the programming algorithm seems to be the
> > same as for SST 49LF020A.
> >
> > I've only tested read so far, i'm a bit reluctant to test
> > erase/programming without a backup BIOS chip :)
>
> You forgot the Signed-off-by for this patch, please repost with that.
> [..]
> As reading works, this is not UNSTESTED. At least PROBE and READ
> should be marked as working.

Thanks for commenting, here is the updated patch:

Signed-off-by: Sven Schnelle

Index: coreboot-v2/util/flashrom/flash.h
===================================================================
--- coreboot-v2/util/flashrom/flash.h	(revision 3846)
+++ coreboot-v2/util/flashrom/flash.h	(working copy)
@@ -356,6 +356,7 @@
 #define SST_39VF040		0xD7
 #define SST_49LF040B		0x50
 #define SST_49LF040		0x51
+#define SST_49LF020		0x61
 #define SST_49LF020A		0x52
 #define SST_49LF080A		0x5B
 #define SST_49LF002A		0x57
Index: coreboot-v2/util/flashrom/flashchips.c
===================================================================
--- coreboot-v2/util/flashrom/flashchips.c	(revision 3846)
+++ coreboot-v2/util/flashrom/flashchips.c	(working copy)
@@ -626,6 +626,12 @@
     probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
    },

+	{"SST", "SST49LF020", SST_ID, SST_49LF020,
+	 256, 16 * 1024,
+	 TEST_OK_PR,
+	 probe_jedec, erase_49lf040, write_49lf040
+	},
+
    {"SST", "SST49LF020A", SST_ID, SST_49LF020A,
     256, 16 * 1024,
     TEST_UNTESTED,

[Uwe Hermann]

On Tue, Jan 06, 2009 at 09:31:21AM +0100, Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle

Thanks, r3850.

Btw, can we mark all the new stuff from your patches as supported in
the wiki, i.e. is all of it tested on hardware?

Uwe.

[Sven Schnelle]

Hi Uwe,

Uwe Hermann  writes:
> Btw, can we mark all the new stuff from your patches as supported in
> the wiki, i.e. is all of it tested on hardware?

Yes, they are tested on hardware - i have three Boards here,

2 with the Intel 5000 Chipset,
1 with AMD 760 Chipset.

The reason for adding the Flash/Chipset support is that i want to port/use
coreboot on these platforms.

Sven.

[Uwe Hermann]

On Wed, Jan 07, 2009 at 01:55:26PM +0100, Sven Schnelle wrote:
> Hi Uwe,
>
> Uwe Hermann  writes:
> > Btw, can we mark all the new stuff from your patches as supported in
> > the wiki, i.e. is all of it tested on hardware?
>
> Yes, they are tested on hardware - i have three Boards here,

OK, wiki updated.
> 2 with the Intel 5000 Chipset,

Is this chipset related to or compatible with the new 631xESB/632xESB/3100
stuff you added in flashrom? Did you test 5000, or 631xESB/632xESB/3100,
or both?
> 1 with AMD 760 Chipset.

Do you mean 780 here?
> The reason for adding the Flash/Chipset support is that i want to port/use
> coreboot on these platforms.

Nice! There's some old AMD-768 code in coreboot-v1, maybe you can use
that as inspiration (no idea if or how well that worked back then).
Those files don't have license headers unfortunately, so you can either
start from scratch with a v2 or even v3 code, or find out who wrote that
code and add the proper license headers (judging from the svn commit log
it should be Eric Biederman, GPL2)...

CC'd Eric...

Uwe.

Uwe Hermann  writes:
> On Wed, Jan 07, 2009 at 01:55:26PM +0100, Sven Schnelle wrote:
> > Hi Uwe,
> >
> > Uwe Hermann  writes:
> > > Btw, can we mark all the new stuff from your patches as supported in
> > > the wiki, i.e. is all of it tested on hardware?
> >
> > Yes, they are tested on hardware - i have three Boards here,
>
> OK, wiki updated.
> > 2 with the Intel 5000 Chipset,
>
> Is this chipset related to or compatible with the new 631xESB/632xESB/3100
> stuff you added in flashrom? Did you test 5000, or 631xESB/632xESB/3100,
> or both?
> > 1 with AMD 760 Chipset.
>
> Do you mean 780 here?
> > The reason for adding the Flash/Chipset support is that i want to port/use
> > coreboot on these platforms.
>
> Nice! There's some old AMD-768 code in coreboot-v1, maybe you can use
> that as inspiration (no idea if or how well that worked back then).
> Those files don't have license headers unfortunately, so you can either

Not necessary the entire project was GPLv2.  Saying it in every file
is redundant and useful, but as I understand it not strictly necessary,
and in certain cases very very annoying.
> start from scratch with a v2 or even v3 code, or find out who wrote that
> code and add the proper license headers (judging from the svn commit log
> it should be Eric Biederman, GPL2)...

Yep.  I wrote it.  The code worked well, there is a cluster or two running it.
It was released late in the life cycle of the hardware because it took a while
to get the last critical bits out of NDA with AMD.

Eric

[Sven Schnelle]

Hi Uwe,

Uwe Hermann  writes:
> On Wed, Jan 07, 2009 at 01:55:26PM +0100, Sven Schnelle wrote:
> > Uwe Hermann  writes:
> > > Btw, can we mark all the new stuff from your patches as supported in
> > > the wiki, i.e. is all of it tested on hardware?
> >
> > Yes, they are tested on hardware - i have three Boards here,
>
> OK, wiki updated.
> > 2 with the Intel 5000 Chipset,
>
> Is this chipset related to or compatible with the new 631xESB/632xESB/3100
> stuff you added in flashrom? Did you test 5000, or 631xESB/632xESB/3100,
> or both?

I should have written Intel 5000/631x/632x/3100 as they are used
together:

$ lspci -tv
-[0000:00]-+-00.0  Intel Corporation 5000P Chipset Memory Controller Hub
           +-02.0-[0000:01-05]--+-00.0-[0000:02-04]--+-00.0-[0000:03]--
           |                    |                    -02.0-[0000:04]--+-00.0  Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper)
           |                    |                                      -00.1  Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper)
           |                    -00.3-[0000:05]----01.0  Adaptec AIC-7892A U160/m
           +-03.0-[0000:06]--
           +-04.0-[0000:07]--+-00.0  ATI Technologies Inc Mobility Radeon HD 3600 Series
           |                 -00.1  ATI Technologies Inc RV635 Audio device [Radeon HD 3600 Series]
           +-05.0-[0000:08]--
           +-06.0-[0000:09]--
           +-07.0-[0000:0a]--
           +-08.0  Intel Corporation 5000 Series Chipset DMA Engine
           +-10.0  Intel Corporation 5000 Series Chipset FSB Registers
           +-10.1  Intel Corporation 5000 Series Chipset FSB Registers
           +-10.2  Intel Corporation 5000 Series Chipset FSB Registers
           +-11.0  Intel Corporation 5000 Series Chipset Reserved Registers
           +-13.0  Intel Corporation 5000 Series Chipset Reserved Registers
           +-15.0  Intel Corporation 5000 Series Chipset FBD Registers
           +-16.0  Intel Corporation 5000 Series Chipset FBD Registers
           +-1c.0-[0000:0b]--
           +-1d.0  Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #1
           +-1d.1  Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #2
           +-1d.2  Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #3
           +-1d.3  Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #4
           +-1d.7  Intel Corporation 631xESB/632xESB/3100 Chipset EHCI USB2 Controller
           +-1e.0-[0000:0c]--
           +-1f.0  Intel Corporation 631xESB/632xESB/3100 Chipset LPC Interface Controller
           +-1f.1  Intel Corporation 631xESB/632xESB IDE Controller
           +-1f.2  Intel Corporation 631xESB/632xESB/3100 Chipset SATA IDE Controller
           -1f.3  Intel Corporation 631xESB/632xESB/3100 Chipset SMBus
           Controller

Actually i have no idea if i'll have any luck getting something done one
that Platform, but i have two of these Boards, Documentation from Intel
seems to be available, so it's worth a try.

(Real reason is that i've seen the great Presentation from Peter Stuge
at the 25. Chaos Communication Congress (25C3). As i have no boards here
which are supported by coreboot now, only chance to play is trying to add
support for the boards i have. ;) )
> > The reason for adding the Flash/Chipset support is that i want to port/use
> > coreboot on these platforms.
>
> Nice! There's some old AMD-768 code in coreboot-v1, maybe you can use
> that as inspiration (no idea if or how well that worked back then).
> Those files don't have license headers unfortunately, so you can either
> start from scratch with a v2 or even v3 code, or find out who wrote that
> code and add the proper license headers (judging from the svn commit log
> it should be Eric Biederman, GPL2)...

Thanks for that hint, will look into that code :)

Sven.