[commit] r6088 - in trunk/src: mainboard/intel/eagleheights southbridge/intel/i3100

[repository service]

Author: oxygene
Date: Thu Nov 18 11:48:15 2010
New Revision: 6088
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6088

Log:
Move register block definitions out of board code into
chipset code (where it belongs)

Signed-off-by: Patrick Georgi 
Acked-by: Patrick Georgi

Modified:
   trunk/src/mainboard/intel/eagleheights/romstage.c
   trunk/src/southbridge/intel/i3100/i3100.h
   trunk/src/southbridge/intel/i3100/i3100_sata.c

Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c	Thu Nov 18 01:46:53 2010	(r6087)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c	Thu Nov 18 11:48:15 2010	(r6088)
@@ -41,16 +41,11 @@
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i3100/i3100.h"
+#include "southbridge/intel/i3100/i3100.h"

#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)

-/* SATA */
-#define SATA_MAP 0x90
-
-#define SATA_MODE_IDE  0x00
-#define SATA_MODE_AHCI 0x01
-
 #define RCBA_RPC   0x0224 /* 32 bit */

#define RCBA_TCTL  0x3000 /*  8 bit */

Modified: trunk/src/southbridge/intel/i3100/i3100.h
==============================================================================
--- trunk/src/southbridge/intel/i3100/i3100.h	Thu Nov 18 01:46:53 2010	(r6087)
+++ trunk/src/southbridge/intel/i3100/i3100.h	Thu Nov 18 11:48:15 2010	(r6088)
@@ -21,6 +21,25 @@
 #define SOUTHBRIDGE_INTEL_I3100_I3100_H
 #include "chip.h"

+#define SATA_CMD     0x04
+#define SATA_PI      0x09
+#define SATA_PTIM    0x40
+#define SATA_STIM    0x42
+#define SATA_D1TIM   0x44
+#define SATA_SYNCC   0x48
+#define SATA_SYNCTIM 0x4A
+#define SATA_IIOC    0x54
+#define SATA_MAP     0x90
+#define SATA_PCS     0x91
+#define SATA_ACR0    0xA8
+#define SATA_ACR1    0xAC
+#define SATA_ATC     0xC0
+#define SATA_ATS     0xC4
+#define SATA_SP      0xD0
+
+#define SATA_MODE_IDE  0x00
+#define SATA_MODE_AHCI 0x01
+
 void i3100_enable(device_t dev);

#endif

Modified: trunk/src/southbridge/intel/i3100/i3100_sata.c
==============================================================================
--- trunk/src/southbridge/intel/i3100/i3100_sata.c	Thu Nov 18 01:46:53 2010	(r6087)
+++ trunk/src/southbridge/intel/i3100/i3100_sata.c	Thu Nov 18 11:48:15 2010	(r6088)
@@ -27,22 +27,6 @@
 #include <device/pci_ops.h>
 #include "i3100.h"

-#define SATA_CMD     0x04
-#define SATA_PI      0x09
-#define SATA_PTIM    0x40
-#define SATA_STIM    0x42
-#define SATA_D1TIM   0x44
-#define SATA_SYNCC   0x48
-#define SATA_SYNCTIM 0x4A
-#define SATA_IIOC    0x54
-#define SATA_MAP     0x90
-#define SATA_PCS     0x91
-#define SATA_ACR0    0xA8
-#define SATA_ACR1    0xAC
-#define SATA_ATC     0xC0
-#define SATA_ATS     0xC4
-#define SATA_SP      0xD0
-
 typedef struct southbridge_intel_i3100_config config_t;

static void sata_init(struct device *dev)