[patch 00/16] ASUS M2V support (v3)

[Tobias Diedrich]

Updated patch series for ASUS M2V support.

I've tried breaking it up a bit more.

[patch 01/16] Add VT8237A device id

[Tobias Diedrich]

This adds the VT8237A LPC device id and the pci_driver struct in
vt8237r_lpc.c

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-11-06 22:28:43.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-06 22:29:48.000000000 +0100
@@ -543,6 +543,12 @@
    .device	= PCI_DEVICE_ID_VIA_VT8237R_LPC,
 };

+static const struct pci_driver lpc_driver_a __pci_driver = {
+	.ops	= &vt8237r_lpc_ops_r,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT8237A_LPC,
+};
+
 static const struct pci_driver lpc_driver_s __pci_driver = {
    .ops	= &vt8237r_lpc_ops_s,
    .vendor	= PCI_VENDOR_ID_VIA,
Index: src/include/device/pci_ids.h
===================================================================
--- src/include/device/pci_ids.h.orig	2010-11-06 22:28:43.000000000 +0100
+++ src/include/device/pci_ids.h	2010-11-06 22:29:48.000000000 +0100
@@ -1226,6 +1226,7 @@
 #define PCI_DEVICE_ID_VIA_K8T890CE_BR	0xb188
 #define PCI_DEVICE_ID_VIA_VT6420_SATA	0x3149
 #define PCI_DEVICE_ID_VIA_VT8237R_LPC	0x3227
+#define PCI_DEVICE_ID_VIA_VT8237A_LPC	0x3337
 #define PCI_DEVICE_ID_VIA_VT8237S_LPC	0x3372
 #define PCI_DEVICE_ID_VIA_VT8237_SATA	0x5372
 #define PCI_DEVICE_ID_VIA_VT8237_VLINK	0x287e

[patch 01/16] Add VT8237A device id

[Rudolf Marek]

Acked-by: Rudolf Marek

Checked in too.

Rudolf

[patch 02/16] Add VT8237A init

[Tobias Diedrich]

This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c
and vt8237r_lpc.c.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237_ctrl.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237_ctrl.c.orig	2010-11-07 12:51:21.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237_ctrl.c	2010-11-07 12:51:28.000000000 +0100
@@ -168,6 +168,75 @@

}

+static void vt8237a_vlink_init(struct device *dev)
+{
+	u8 reg;
+	device_t devfun7;
+
+	devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+				  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
+	/* No pairing NB was found. */
+	if (!devfun7)
+		return;
+
+	/*
+	 * This init code is valid only for the VT8237A! For different
+	 * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different
+	 * init code is required.
+	 *
+	 * FIXME: This is based on vt8237r_vlink_init() in
+	 *        k8t890/k8t890_ctrl.c and modified to fit what the AMI
+	 *        BIOS on my M2V wrote to these registers (by looking
+	 *        at lspci -nxxx output).
+	 *        Works for me.
+	 */
+
+	/* disable auto disconnect */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg &= ~0x4;
+	pci_write_config8(devfun7, 0x42, reg);
+
+	/* NB part setup */
+	pci_write_config8(devfun7, 0xb5, 0x88);
+	pci_write_config8(devfun7, 0xb6, 0x88);
+	pci_write_config8(devfun7, 0xb7, 0x61);
+
+	reg = pci_read_config8(devfun7, 0xb4);
+	reg |= 0x11;
+	pci_write_config8(devfun7, 0xb4, reg);
+
+	pci_write_config8(devfun7, 0xb0, 0x6);
+	pci_write_config8(devfun7, 0xb1, 0x1);
+
+	/* SB part setup */
+	pci_write_config8(dev, 0xb7, 0x50);
+	pci_write_config8(dev, 0xb9, 0x88);
+	pci_write_config8(dev, 0xba, 0x8a);
+	pci_write_config8(dev, 0xbb, 0x88);
+
+	reg = pci_read_config8(dev, 0xbd);
+	reg |= 0x3;
+	reg &= ~0x4;
+	pci_write_config8(dev, 0xbd, reg);
+
+	reg = pci_read_config8(dev, 0xbc);
+	reg &= ~0x7;
+	pci_write_config8(dev, 0xbc, reg);
+
+	pci_write_config8(dev, 0x48, 0x23);
+
+	/* enable auto disconnect, for STPGNT and HALT */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg |= 0x7;
+	pci_write_config8(devfun7, 0x42, reg);
+}
+
 static void ctrl_enable(struct device *dev)
 {
    /* Enable the 0:13 and 0:13.1. */
@@ -193,6 +262,12 @@
    	vt8237s_vlink_init(dev);
    }

+	devsb = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
+	if (devsb) {
+		vt8237a_vlink_init(dev);
+	}
+
    /* Configure PCI1 and copy mirror registers from D0F3. */
    vt8237_cfg(dev);
    dump_south(dev);
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-11-07 12:51:21.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-07 12:52:23.000000000 +0100
@@ -319,6 +319,58 @@
    printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }

+static void vt8237a_init(struct device *dev)
+{
+	/*
+	 * FIXME: This is based on vt8237s_init() and the values the AMI
+	 *        BIOS on my M2V wrote to these registers (by loking
+	 *        at lspci -nxxx output).
+	 *        Works for me.
+	 */
+	u32 tmp;
+
+	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
+	tmp = pci_read_config8(dev, 0x4f);
+	tmp |= 0x08;
+	pci_write_config8(dev, 0x4f, tmp);
+
+	/*
+	 * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
+	 * bit5: usb power control lines as gpio
+	 */
+	pci_write_config8(dev, 0xe4, 0x24);
+	/*
+	 * Enable APIC wakeup from INTH
+	 * Enable SATA LED, disable special CPU Frequency Change -
+	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 */
+	pci_write_config8(dev, 0xe5, 0x69);
+
+	/* Reduce further the STPCLK/LDTSTP signal to 5us. */
+	pci_write_config8(dev, 0xec, 0x4);
+
+	/* Host Bus Power Management Control, maybe not needed */
+	pci_write_config8(dev, 0x8c, 0x5);
+
+	/* Enable HPET at VT8237R_HPET_ADDR. */
+	pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+
+	southbridge_init_common(dev);
+
+	/* Share INTE-INTH with INTA-INTD for simplicity */
+	pci_write_config8(dev, 0x46, 0x00);
+
+	/* FIXME: Intel needs more bit set for C2/C3. */
+
+	/*
+	 * Allow SLP# signal to assert LDTSTOP_L.
+	 * Will work for C3 and for FID/VID change.
+	 */
+	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+
+	dump_south(dev);
+}
+
 static void vt8237s_init(struct device *dev)
 {
    u32 tmp;
@@ -537,6 +589,14 @@
    .scan_bus		= scan_static_bus,
 };

+static const struct device_operations vt8237r_lpc_ops_a = {
+	.read_resources		= vt8237r_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= vt8237a_init,
+	.scan_bus		= scan_static_bus,
+};
+
 static const struct pci_driver lpc_driver_r __pci_driver = {
    .ops	= &vt8237r_lpc_ops_r,
    .vendor	= PCI_VENDOR_ID_VIA,
@@ -544,7 +604,7 @@
 };

static const struct pci_driver lpc_driver_a __pci_driver = {
-	.ops	= &vt8237r_lpc_ops_r,
+	.ops	= &vt8237r_lpc_ops_a,
    .vendor	= PCI_VENDOR_ID_VIA,
    .device	= PCI_DEVICE_ID_VIA_VT8237A_LPC,
 };

[patch 02/16] Add VT8237A init

[Rudolf Marek]

Acked-by: Rudolf Marek

Checked in too.

Rudolf

[patch 03/16] Introduce get_vt8237_lpc() function

[Tobias Diedrich]

Instead of duplicating the pci_locate_device calls multiple times,
add a get_vt8237_lpc() function.

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig	2010-11-06 22:26:22.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-11-06 22:26:24.000000000 +0100
@@ -134,6 +134,21 @@

#define PSONREADY_TIMEOUT 0x7fffffff

+static device_t get_vt8237_lpc(void)
+{
+	device_t dev;
+
+	/* Power management controller */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+	if (dev != PCI_DEV_INVALID)
+		return dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+	return dev;
+}
+
 /**
  * Enable the SMBus on VT8237R-based systems.
  */
@@ -143,15 +158,9 @@
    int loops;

/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			die("Power management controller not found\n");
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		die("Power management controller not found\n");

/* Make sure the RTC power well is up before touching smbus. */
    loops = 0;
@@ -292,15 +299,9 @@
    device_t dev;

/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			return;
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		return;

/* ROM decode last 1MB FFC00000 - FFFFFFFF. */
    pci_write_config8(dev, 0x41, 0x7f);
@@ -316,15 +317,9 @@
    print_debug("IN TEST WAKEUP\n");

/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			die("Power management controller not found\n");
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		die("Power management controller not found\n");

/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
    pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);

[patch 04/16] Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid().

[Tobias Diedrich]

Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid() too.
I broke this out into a seperate part to keep the other half as
straight-forward as possible.

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig	2010-11-06 22:40:21.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-11-06 22:40:22.000000000 +0100
@@ -244,17 +244,15 @@
 void vt8237_sb_enable_fid_vid(void)
 {
    device_t dev, devctl;
+	u16 devid;

/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			return;
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		return;

+	devid = pci_read_config16(dev, PCI_DEVICE_ID);
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
    	devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
    				   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);

[patch 04/16] Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid().

[Rudolf Marek]

Acked-by: Rudolf Marek

And also commited as 6041.

R.

[patch 05/16] Add VT8237A id to vt8237r_early_smbus

[Tobias Diedrich]

This adds the VT8237A LPC pci_locate_device call in vt8237r_early_smbus.c
Depends on the "Introduce get_vt8237_lpc() function" patch.

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig	2010-11-03 23:32:52.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-11-03 23:32:54.000000000 +0100
@@ -146,6 +146,11 @@

dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
    			PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+	if (dev != PCI_DEV_INVALID)
+		return dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
    return dev;
 }

[patch 05/16] Add VT8237A id to vt8237r_early_smbus

[Rudolf Marek]

Acked-by: Rudolf Marek 
As 6042.

Rudolf

[patch 06/16] Add VT8237A init to vt8237r_early_smbus

[Tobias Diedrich]

Depends on the "Introduce get_vt8237_lpc() function" and
"Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches.

This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c
I ran some tests and apparently both the

|			/* So the chip knows we are on AMD. */
|			pci_write_config8(devctl, 0x7c, 0x7f);

and

|	/*
|	 * Allow SLP# signal to assert LDTSTOP_L.
|	 * Will work for C3 and for FID/VID change.
|	 */
|	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);

in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal)
fid/vid change error on boot.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig	2010-11-06 22:30:40.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-11-06 22:30:41.000000000 +0100
@@ -257,19 +257,30 @@
    	return;

devid = pci_read_config16(dev, PCI_DEVICE_ID);
-	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
-		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);

-		if (devctl == PCI_DEV_INVALID)
-			return;
+	/* generic setup */
+
+	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
+	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+
+	/* Enable ACPI accessm RTC signal gated with PSON. */
+	pci_write_config8(dev, 0x81, 0x84);
+
+	/* chipset-specific parts */

-		/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
-		pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+	/* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC ||
+	    devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) {
+		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);

-		/* Enable ACPI accessm RTC signal gated with PSON. */
-		pci_write_config8(dev, 0x81, 0x84);
+		if (devctl != PCI_DEV_INVALID) {
+			/* So the chip knows we are on AMD. */
+			pci_write_config8(devctl, 0x7c, 0x7f);
+		}
+	}

+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
    	/*
    	 * Allow SLP# signal to assert LDTSTOP_L.
    	 * Will work for C3 and for FID/VID change.
@@ -280,17 +291,10 @@
    	/* Reduce further the STPCLK/LDTSTP signal to 5us. */
    	pci_write_config8(dev, 0xec, 0x4);

-		/* So the chip knows we are on AMD. */
-		pci_write_config8(devctl, 0x7c, 0x7f);
-
    	return;
    }

-	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
-	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
-
-	/* Enable ACPI accessm RTC signal gated with PSON. */
-	pci_write_config8(dev, 0x81, 0x84);
+	/* VT8237R and VT8237A */

/*
     * Allow SLP# signal to assert LDTSTOP_L.

[patch 06/16] Add VT8237A init to vt8237r_early_smbus

[Rudolf Marek]

Acked-by: Rudolf Marek

As 6043.

Rudolf

[patch 07/16] Add pointer to PCIe bridge documentation.

[Tobias Diedrich]

Add pointer to public PCIe bridge documentation on
http://linux.via.com.tw/ as VX800 seems to be compatible.

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/k8t890/k8t890_pcie.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_pcie.c.orig	2010-11-03 14:53:07.000000000 +0100
+++ src/southbridge/via/k8t890/k8t890_pcie.c	2010-11-03 15:51:23.000000000 +0100
@@ -24,6 +24,12 @@
 #include <device/pci_ids.h>
 #include "k8t890.h"

+/*
+ * Note:
+ * The pcie bridges are similar to the VX800 ones documented at
+ * http://linux.via.com.tw/
+ */
+
 static void peg_init(struct device *dev)
 {
    u8 reg;

[patch 07/16] Add pointer to PCIe bridge documentation.

[Rudolf Marek]

Acked-by: Rudolf Marek 
And commited.

R.

[patch 08/16] Comment clarifications.

[Tobias Diedrich]

Comment clarifications.

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/k8t890/k8t890_ctrl.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_ctrl.c.orig	2010-11-07 12:51:16.000000000 +0100
+++ src/southbridge/via/k8t890/k8t890_ctrl.c	2010-11-07 12:52:38.000000000 +0100
@@ -154,7 +154,11 @@

pci_write_config8(dev, 0x47, 0x30);

-	/* VT8237R specific configuration  other SB are done in their own directories */
+	/*
+	 * VT8237R specific configuration,
+	 * other SB are done in their own directories:
+	 * VT8237A and VT8237S are handled in vt8237_ctrl.c
+	 */

device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
    				 PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-11-07 12:52:23.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-07 12:52:38.000000000 +0100
@@ -460,7 +460,18 @@
    /* I/O recovery time, default IDE routing */
    pci_write_config8(dev, 0x4c, 0x04);

-	/* ROM memory cycles go to LPC. */
+	/*
+	 * Bit | Meaning
+	 *   7 | 1: Only ROM memory cycles go to LPC instead of all memory
+	 *     |    cycles.
+	 *   6 | 0: Internal ISA cycles do not arbitrate with secondary IDE
+	 *   5 | 0: Disable LPC RTC
+	 *   4 | 0: Disable LPC Keyboard
+	 *   3 | 0: Disable Port 0x62/0x66 to LPC
+	 *   2 | 0: Disable Port 0x62/0x66 MCCS# chipselect decoding
+	 *   1 | 0: Disable A20M# signal (signal not asserted)
+	 *   0 | 0: Disable NMI on PCI parity error
+	 */
    pci_write_config8(dev, 0x59, 0x80);

/*
@@ -482,7 +493,18 @@
    /* I/O recovery time, default IDE routing */
    pci_write_config8(dev, 0x4c, 0x44);

-	/* ROM memory cycles go to LPC. */
+	/*
+	 * Bit | Meaning
+	 *   7 | 1: Only ROM memory cycles go to LPC instead of all memory
+	 *     |    cycles.
+	 *   6 | 0: Internal ISA cycles do not arbitrate with secondary IDE
+	 *   5 | 0: Disable LPC RTC
+	 *   4 | 0: Disable LPC Keyboard
+	 *   3 | 0: Disable Port 0x62/0x66 to LPC
+	 *   2 | 0: Disable Port 0x62/0x66 MCCS# chipselect decoding
+	 *   1 | 0: Disable A20M# signal (signal not asserted)
+	 *   0 | 0: Disable NMI on PCI parity error
+	 */
    pci_write_config8(dev, 0x59, 0x80);

/*

[patch 09/16] Add minimal ASUS M2V support

[Tobias Diedrich]

This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.

Signed-off-by: Tobias Diedrich

---

Index: src/mainboard/asus/Kconfig
===================================================================
--- src/mainboard/asus/Kconfig.orig	2010-11-07 01:19:21.000000000 +0100
+++ src/mainboard/asus/Kconfig	2010-11-07 01:44:51.000000000 +0100
@@ -25,6 +25,8 @@
    bool "A8N-E"
 config BOARD_ASUS_A8V_E_SE
    bool "A8V-E SE"
+config BOARD_ASUS_M2V
+	bool "M2V"
 config BOARD_ASUS_M2V_MX_SE
    bool "M2V-MX SE"
 config BOARD_ASUS_M4A785M
@@ -50,6 +52,7 @@

source "src/mainboard/asus/a8n_e/Kconfig"
 source "src/mainboard/asus/a8v-e_se/Kconfig"
+source "src/mainboard/asus/m2v/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
 source "src/mainboard/asus/m4a785-m/Kconfig"
 source "src/mainboard/asus/mew-am/Kconfig"
Index: src/mainboard/asus/m2v/devicetree.cb
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/devicetree.cb	2010-11-07 01:44:51.000000000 +0100
@@ -0,0 +1,74 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device lapic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_AM2			# CPU
+      device lapic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0xc0"	# Enable SB functions
+          register "fn_ctrl_hi" = "0x0d"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            chip superio/ite/it8712f		# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.2 off end		# Com2 (N/A on this board)
+              device pnp 2e.3 on		# Lpt1
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 3
+              end
+              device pnp 2e.4 on		# Environment controller
+                io 0x60 = 0xd00
+                io 0x62 = 0xc00
+                irq 0x70 = 0x00
+              end
+              device pnp 2e.5 off end		# PS/2 keyboard
+              device pnp 2e.6 off end		# PS/2 mouse
+              device pnp 2e.7 off end		# GPIO config
+              device pnp 2e.8 off end		# Midi port
+              device pnp 2e.9 off end		# Game port
+              device pnp 2e.a off end		# IR
+            end
+          end
+          device pci 12.0 off end		# VIA LAN (off, other chip used)
+          device pci 13.0 on end		# br
+          device pci 13.1 on end		# br2, need to have it here to discover it
+        end
+        chip southbridge/via/k8t890		# "Southbridge" K8T890
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end
Index: src/mainboard/asus/m2v/Kconfig
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/Kconfig	2010-11-07 12:20:29.000000000 +0100
@@ -0,0 +1,77 @@
+if BOARD_ASUS_M2V
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_AM2
+	select DIMM_DDR2
+	select QRANK_DIMM_SUPPORT
+	select HAVE_OPTION_TABLE
+	select K8_HT_FREQ_1G_SUPPORT
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_VIA_VT8237R
+	select SOUTHBRIDGE_VIA_K8T890
+	select SUPERIO_ITE_IT8712F
+	select CACHE_AS_RAM
+	select BOARD_ROMSIZE_KB_512
+	select RAMINIT_SYSINFO
+	select TINY_BOOTBLOCK
+
+config MAINBOARD_DIR
+	string
+	default asus/m2v
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xcc000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x1000
+
+config APIC_ID_OFFSET
+	hex
+	default 0x10
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "M2V"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0
+
+config MAX_CPUS
+	int
+	default 2
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+config HEAP_SIZE
+	hex
+	default 0x40000
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x20
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1043
+
+endif # BOARD_ASUS_M2V
Index: src/mainboard/asus/m2v/romstage.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/romstage.c	2010-11-07 01:44:51.000000000 +0100
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * (Written by Yinghai Lu  for AMD)
+ * Copyright (C) 2006 MSI
+ * (Written by Bingxun Shi  for MSI)
+ * Copyright (C) 2008 Rudolf Marek 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+unsigned int get_sbdn(unsigned bus);
+
+/* Used by init_cpus and fidvid */
+#define SET_FIDVID 1
+
+/* If we want to wait for core1 done before DQS training, set it to 0. */
+#define SET_FIDVID_CORE0_ONLY 1
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
+#define IT8712F_GPIO_BASE		0x0a20
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+// defines S3_NVRAM_EARLY:
+#include "southbridge/via/k8t890/k8t890_early_car.c"
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "lib/generic_sdram.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+void soft_reset(void)
+{
+	uint8_t tmp;
+
+	set_bios_reset();
+	print_debug("soft reset\n");
+
+	/* PCI reset */
+	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
+	tmp |= 0x01;
+	/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
+	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+
+	while (1) {
+		/* daisy daisy ... */
+		hlt();
+	}
+}
+
+unsigned int get_sbdn(unsigned bus)
+{
+	device_t dev;
+
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+					PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
+	return (dev >> 15) & 0x1f;
+}
+
+struct gpio_init_val {
+	u8 addr;
+	u8 val;
+};
+
+static const struct gpio_init_val gpio_init_data[] = {
+	/* multi-function pin selection */
+	{ 0x25, 0x00 },
+	{ 0x28, 0x00 }, /* gp46 is infrared receive input */
+	{ 0x29, 0x40 }, /* reserved value?!? */
+	{ 0x2a, 0x00 },
+	{ 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */
+	/* gpio i/o port base */
+	{ 0x62, IT8712F_GPIO_BASE >> 8 },
+	{ 0x63, IT8712F_GPIO_BASE & 0xff },
+	/* 0xb8 - 0xbc: gpio pull-up enable */
+	{ 0xb8, 0x00 },
+	/* 0xc0 - 0xc4: gpio alternate function select */
+	{ 0xc0, 0x00 },
+	{ 0xc3, 0x00 },
+	{ 0xc4, 0xc0 },
+	/* 0xc8 - 0xcc: gpio output enable */
+	{ 0xc8, 0x00 },
+	{ 0xcb, 0x00 },
+	{ 0xcc, 0xc0 },
+	/* end of list */
+	{ 0, 0 },
+};
+
+static void m2v_it8712f_gpio_init(void)
+{
+	const struct gpio_init_val *giv;
+
+	printk(BIOS_SPEW, "it8712f gpio init...\n");
+
+	/*
+	 * it8712f gpio config
+	 *
+	 * Most importantly this switches pin 91 from
+	 * PCIRSTIN# to VIN7.
+	 * Note that only PCIRST3# and PCIRST5# are affected
+	 * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
+	 * direct buffers of #LRESET (low pin count bus reset).
+	 * If this is not done All PCIRST are in reset state and the
+	 * pcie slots don't initialize.
+	 *
+	 * pci reset handling:
+	 * pin 91: VIN7 (alternate PCIRSTIN#)
+	 * pin 48: PCIRST5# / gpio port 5 bit 0
+	 * pin 84: PCIRST4# / gpio port 1 bit 0
+	 * pin 31: PCIRST1# / gpio port 1 bit 4
+	 * pin 33: PCIRST2# / gpio port 1 bit 2
+	 * pin 34: PCIRST3# / gpio port 1 bit 1
+	 *
+	 * PCIRST[0-5]# are connected as follows:
+	 * pcirst1# -> pci bus
+	 * pcirst2# -> ide bus
+	 * pcirst3# -> pcie devices
+	 * pcirst4# -> pcie graphics
+	 * pcirst5# -> maybe n/c (untested)
+	 *
+	 * For software control of PCIRST[1-5]#:
+	 * 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control)
+	 * 0x25=0x17 (select gpio function)
+	 * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
+	 * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
+	 */
+	it8712f_enter_conf();
+	giv = gpio_init_data;
+	while (giv->addr) {
+		printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
+				giv->addr, giv->val);
+		it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
+		giv++;
+	}
+	it8712f_exit_conf();
+}
+
+static void m2v_bus_init(void)
+{
+	device_t dev;
+
+	printk(BIOS_SPEW, "m2v_bus_init\n");
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_K8T890CF_0), 0);
+	pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_K8T890CF_5), 0);
+	/*
+	 * bit | meaning
+	 * 6   | 0: hide scratch register function 0:0.6 (we don't use it)
+	 * 5   | 1: enable pcie bridge 0:2.0
+	 * 4   | 0: hide   pcie bridge 0:3.3 (not connected)
+	 * 3   | 1: enable pcie bridge 0:3.2
+	 * 2   | 1: enable pcie bridge 0:3.1
+	 * 1   | 1: enable pcie bridge 0:3.0
+	 */
+	pci_write_config8(dev, 0xf0, 0x2e);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr[] = {
+		// Node 0
+		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
+		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		// Node 1
+		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
+		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+	};
+	unsigned bsp_apicid = 0;
+	int needs_reset = 0;
+	struct sys_info *sysinfo =
+	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+	it8712f_24mhz_clkin();
+	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	it8712f_kill_watchdog();
+	uart_init();
+	console_init();
+	enable_rom_decode();
+	m2v_bus_init();
+	m2v_it8712f_gpio_init();
+
+	printk(BIOS_INFO, "now booting... \n");
+
+	if (bist == 0)
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+
+	/* Halt if there was a built in self test failure. */
+	report_bist_failure(bist);
+	setup_default_resource_map();
+	setup_coherent_ht_domain();
+	wait_all_core0_started();
+
+	printk(BIOS_INFO, "now booting... All core 0 started\n");
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* It is said that we should start core1 after all core0 launched. */
+	start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+	init_timer();
+	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
+
+	needs_reset = optimize_link_coherent_ht();
+	print_debug_hex8(needs_reset);
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	print_debug_hex8(needs_reset);
+	needs_reset |= k8t890_early_setup_ht();
+	print_debug_hex8(needs_reset);
+
+	if (needs_reset) {
+		printk(BIOS_DEBUG, "ht reset -\n");
+		soft_reset();
+		printk(BIOS_DEBUG, "FAILED!\n");
+	}
+
+	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
+	/* allow LDT STOP asserts */
+	vt8237_sb_enable_fid_vid();
+
+	enable_fid_change();
+	print_debug("after enable_fid_change\n");
+
+	init_fidvid_bsp(bsp_apicid);
+
+	/* Stop the APs so we can start them later in init. */
+	allow_all_aps_stop(bsp_apicid);
+
+	/* It's the time to set ctrl now. */
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	enable_smbus();
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+	post_cache_as_ram();
+}
+
Index: src/mainboard/asus/m2v/cmos.layout
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/cmos.layout	2010-11-07 01:44:51.000000000 +0100
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
Index: src/mainboard/asus/m2v/chip.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/chip.h	2010-11-07 01:44:51.000000000 +0100
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
Index: src/mainboard/asus/m2v/mainboard.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/mainboard.c	2010-11-07 01:44:51.000000000 +0100
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Tobias Diedrich 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("ASUS M2V")
+};

[patch 09/16] Add minimal ASUS M2V support

[Rudolf Marek]

Looks good.

Acked-by: Rudolf Marek

In as 6044.

Rudolf

[patch 10/16] Add M2V pirq table

[Tobias Diedrich]

Add pirq table for ASUS M2V.

Signed-off-by: Tobias Diedrich

---

Index: src/mainboard/asus/m2v/irq_tables.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/irq_tables.c	2010-11-07 12:51:08.000000000 +0100
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Tobias Diedrich 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ * IRQ Routing Table
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+ */
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <device/pci_ids.h>
+
+/* Free irqs are 3, 5, 10 and 11 */
+#define IRQBM ((1<<3)|(1<<5)|(1<<10)|(1<<11))
+
+#define LNKA 1
+#define LNKB 2
+#define LNKC 3
+#define LNKD 4
+
+/*
+ * For simplicity map LNK[E-H] to LNK[A-D].
+ * This also means we are 82C596 compatible.
+ * Needs 0:11.0 0x46[4] set to 0.
+ */
+#define LNKE 1
+#define LNKF 2
+#define LNKG 3
+#define LNKH 4
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE, /* u32 signature */
+	PIRQ_VERSION,   /* u16 version   */
+	32+16*CONFIG_IRQ_SLOT_COUNT,        /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+	0,           /* Where the interrupt router lies (bus) */
+	(0x11<<3)|0, /* Where the interrupt router lies (dev) */
+	0,           /* IRQs devoted exclusively to PCI usage */
+	PCI_VENDOR_ID_VIA,         /* Compatible Vendor (VIA) */
+	PCI_DEVICE_ID_VIA_82C596,  /* Compatible Device (82C596) */
+	0,           /* Miniport data */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x5f,        /*  u8 checksum, this has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		/* peg bridge */
+		{0x00, (0x02 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
+		/* pcie bridge */
+		{0x00, (0x03 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
+		/* sata/ide */
+		{0x00, (0x0f << 3) | 0x0, {{0x00, 0x0000}, {LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		/* usb */
+		{0x00, (0x10 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
+		/* agp bus? */
+		{0x01, (0x00 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
+		/* pcie graphics */
+		{0x02, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x6, 0x0},
+		/* onboard pcie atl1 ethernet */
+		{0x03, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
+		/* pcie slot */
+		{0x04, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x5, 0x0},
+		/* onboard marvell mv6121 sata */
+		{0x05, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
+		/* Azalia HDAC */
+		{0x06, (0x01 << 3) | 0x0, {{LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		/* PCI slots */
+		{0x07, (0x06 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x1, 0x0},
+		{0x07, (0x07 << 3) | 0x0, {{LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}}, 0x2, 0x0},
+		{0x07, (0x08 << 3) | 0x0, {{LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}}, 0x3, 0x0},
+		{0x07, (0x09 << 3) | 0x0, {{LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}}, 0x4, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
Index: src/mainboard/asus/m2v/Kconfig
===================================================================
--- src/mainboard/asus/m2v/Kconfig.orig	2010-11-07 12:44:03.000000000 +0100
+++ src/mainboard/asus/m2v/Kconfig	2010-11-07 12:44:03.000000000 +0100
@@ -17,6 +17,7 @@
    select BOARD_ROMSIZE_KB_512
    select RAMINIT_SYSINFO
    select TINY_BOOTBLOCK
+	select HAVE_PIRQ_TABLE

config MAINBOARD_DIR
    string
@@ -74,4 +75,8 @@
    hex
    default 0x1043

+config IRQ_SLOT_COUNT
+	int
+	default 14
+
 endif # BOARD_ASUS_M2V

[patch 10/16] Add M2V pirq table

[Rudolf Marek]

Acked-by: Rudolf Marek

And commited too.

Rudolf

[patch 11/16] Add M2V mptable

[Tobias Diedrich]

Add mptable for ASUS M2V.

Signed-off-by: Tobias Diedrich

---

Index: src/mainboard/asus/m2v/mptable.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/mptable.c	2010-11-06 23:54:10.000000000 +0100
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek 
+ * Copyright (C) 2010 Tobias Diedrich 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8t890.h"
+
+static void smp_write_intsrc_pci(struct mp_config_table *mc,
+	unsigned char srcbus, unsigned char srcbusirq,
+	unsigned char dstapic, unsigned char dstirq)
+{
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+			srcbus, srcbusirq, dstapic, dstirq);
+}
+
+static void *smp_write_config_table(void *v)
+{
+	static const char sig[4] = "PCMP";
+	static const char oem[8] = "COREBOOT";
+	static const char productid[12] = "M2V         ";
+	struct mp_config_table *mc;
+	int bus_isa = 42;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	memset(mc, 0, sizeof(*mc));
+
+	memcpy(mc->mpc_signature, sig, sizeof(sig));
+	mc->mpc_length = sizeof(*mc); /* Initially just the header. */
+	mc->mpc_spec = 0x04;
+	mc->mpc_checksum = 0; /* Not yet computed. */
+	memcpy(mc->mpc_oem, oem, sizeof(oem));
+	memcpy(mc->mpc_productid, productid, sizeof(productid));
+	mc->mpc_oemptr = 0;
+	mc->mpc_oemsize = 0;
+	mc->mpc_entry_count = 0; /* No entries yet. */
+	mc->mpc_lapic = LAPIC_ADDR;
+	mc->mpe_length = 0;
+	mc->mpe_checksum = 0;
+	mc->reserved = 0;
+
+	smp_write_processors(mc);
+
+	/* Bus:		Bus ID	Type */
+	smp_write_bus(mc, 0, "PCI   "); /* root bus */
+	smp_write_bus(mc, 1, "PCI   "); /* agp? */
+	smp_write_bus(mc, 2, "PCI   "); /* pcie x16 */
+	smp_write_bus(mc, 3, "PCI   "); /* pcie x1 */
+	smp_write_bus(mc, 4, "PCI   "); /* pcie x1 */
+	smp_write_bus(mc, 5, "PCI   "); /* pcie x1 */
+	smp_write_bus(mc, 6, "PCI   "); /* azalia audio */
+	smp_write_bus(mc, 7, "PCI   "); /* pci */
+	smp_write_bus(mc, bus_isa, "ISA   ");
+
+	/* I/O APICs:	APIC ID	Version	State		Address */
+	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR);
+	smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE);
+
+	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
+
+	/* agp? bridge */
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13);
+
+	/* peg bridge */
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+	/* pex bridge */
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
+
+	/* SATA / IDE */
+	smp_write_intsrc_pci(mc, 0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x15);
+
+	/* USB */
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14);
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16);
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17);
+
+	/* PCIE graphics */
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+	/* onboard PCIE atl1 ethernet */
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
+
+	/* PCIE slot */
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
+
+	/* onboard marvell mv6121 sata */
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
+
+	/* azalia HDCA */
+	smp_write_intsrc_pci(mc, 6,  (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11);
+
+	/* pci slot 1 */
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13);
+
+	/* pci slot 2 */
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13);
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10);
+
+	/* pci slot 3 */
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13);
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11);
+
+	/* pci slot 4 */
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13);
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
+
+	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
+	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums. */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
+						mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/asus/m2v/Kconfig
===================================================================
--- src/mainboard/asus/m2v/Kconfig.orig	2010-11-06 23:53:34.000000000 +0100
+++ src/mainboard/asus/m2v/Kconfig	2010-11-06 23:54:10.000000000 +0100
@@ -18,6 +18,7 @@
    select RAMINIT_SYSINFO
    select TINY_BOOTBLOCK
    select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE

config MAINBOARD_DIR
    string

[patch 11/16] Add M2V mptable

[Tobias Diedrich]

Updated for recent mptable_init().
Add mptable for ASUS M2V.

Signed-off-by: Tobias Diedrich

---

Index: src/mainboard/asus/m2v/mptable.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/mptable.c	2010-11-09 23:20:36.000000000 +0100
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek 
+ * Copyright (C) 2010 Tobias Diedrich 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8t890.h"
+
+static void smp_write_intsrc_pci(struct mp_config_table *mc,
+	unsigned char srcbus, unsigned char srcbusirq,
+	unsigned char dstapic, unsigned char dstirq)
+{
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+			srcbus, srcbusirq, dstapic, dstirq);
+}
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa = 42;
+
+	mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, "M2V         ", LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	/* Bus:		Bus ID	Type */
+	smp_write_bus(mc, 0, "PCI   "); /* root bus */
+	smp_write_bus(mc, 1, "PCI   "); /* agp? */
+	smp_write_bus(mc, 2, "PCI   "); /* pcie x16 */
+	smp_write_bus(mc, 3, "PCI   "); /* pcie x1 */
+	smp_write_bus(mc, 4, "PCI   "); /* pcie x1 */
+	smp_write_bus(mc, 5, "PCI   "); /* pcie x1 */
+	smp_write_bus(mc, 6, "PCI   "); /* azalia audio */
+	smp_write_bus(mc, 7, "PCI   "); /* pci */
+	smp_write_bus(mc, bus_isa, "ISA   ");
+
+	/* I/O APICs:	APIC ID	Version	State		Address */
+	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR);
+	smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE);
+
+	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
+
+	/* agp? bridge */
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13);
+
+	/* peg bridge */
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+	/* pex bridge */
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
+	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
+
+	/* SATA / IDE */
+	smp_write_intsrc_pci(mc, 0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x15);
+
+	/* USB */
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14);
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16);
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17);
+
+	/* PCIE graphics */
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
+	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+	/* onboard PCIE atl1 ethernet */
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
+	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
+
+	/* PCIE slot */
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
+	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
+
+	/* onboard marvell mv6121 sata */
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
+	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
+
+	/* azalia HDCA */
+	smp_write_intsrc_pci(mc, 6,  (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11);
+
+	/* pci slot 1 */
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13);
+
+	/* pci slot 2 */
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13);
+	smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10);
+
+	/* pci slot 3 */
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12);
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13);
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11);
+
+	/* pci slot 4 */
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13);
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11);
+	smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
+
+	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
+	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums. */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
+						mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/asus/m2v/Kconfig
===================================================================
--- src/mainboard/asus/m2v/Kconfig.orig	2010-11-09 23:18:30.000000000 +0100
+++ src/mainboard/asus/m2v/Kconfig	2010-11-09 23:18:32.000000000 +0100
@@ -18,6 +18,7 @@
    select RAMINIT_SYSINFO
    select TINY_BOOTBLOCK
    select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE

config MAINBOARD_DIR
    string

[patch 11/16] Add M2V mptable

[Uwe Hermann]

On Tue, Nov 09, 2010 at 11:34:42PM +0100, Tobias Diedrich wrote:
> Updated for recent mptable_init().
> Add mptable for ASUS M2V.
>
> Signed-off-by: Tobias Diedrich

Thanks, r6059.

Uwe.

[patch 12/16] Add M2V basic ACPI support.

[Tobias Diedrich]

Add acpi tables and dsdt.

Signed-off-by: Tobias Diedrich

---

Index: src/mainboard/asus/m2v/acpi_tables.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/acpi_tables.c	2010-11-07 12:52:52.000000000 +0100
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer .
+ * ACPI FADT, FACS, and DSDT table support added by
+ *
+ * Copyright (C) 2004 Stefan Reinauer 
+ * Copyright (C) 2005 Nick Barker 
+ * Copyright (C) 2007, 2008 Rudolf Marek 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8t890.h"
+#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include <cpu/amd/model_fxx_powernow.h>
+
+extern const unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	struct resource *res;
+
+	dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0);
+	if (!dev)
+		return current;
+
+	res = find_resource(dev, K8T890_MMCONFIG_MBAR);
+	if (res) {
+		current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
+				current, res->base, 0x0, 0x0, 0xff);
+	}
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	unsigned int gsi_base = 0x18;
+
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB IOAPIC. */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				VT8237R_APIC_ID, IO_APIC_ADDR, 0);
+
+	/* Write NB IOAPIC. */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
+
+	/* IRQ9 ACPI active low. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+	/* IRQ0 -> APIC IRQ2. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0x0);
+
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapic_nmis(current,
+			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	k8acpi_write_vars();
+	amd_model_fxx_generate_powernow(0, 0, 0);
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_srat_t *srat;
+	acpi_rsdt_t *rsdt;
+	acpi_mcfg_t *mcfg;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_slit_t *slit;
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	/* Align ACPI tables to 16 byte. */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT table. */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* Clear all table memory. */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* We explicitly add these tables later on: */
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+
+	/* we should align FACS to 64B as per ACPI specs */
+
+	current = ALIGN(current, 64);
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
+	dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET timers Linux wants an MADT. */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current+=slit->header.length;
+	acpi_add_table(rsdp,slit);
+
+	/* SSDT */
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+
+	return current;
+}
Index: src/mainboard/asus/m2v/dsdt.asl
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/dsdt.asl	2010-11-07 12:58:28.000000000 +0100
@@ -0,0 +1,534 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker 
+ * Copyright (C) 2007 Rudolf Marek 
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Tobias Diedrich 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+#define LNKA INTA
+#define LNKB INTB
+#define LNKC INTC
+#define LNKD INTD
+
+/*
+ * For simplicity map LNK[E-H] to LNK[A-D].
+ * This also means we are 82C596 compatible.
+ * Needs 0:11.0 0x46[4] set to 0.
+ */
+#define LNKE INTA
+#define LNKF INTB
+#define LNKG INTC
+#define LNKH INTD
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
+{
+	Name(APIC, 0)		// 0=>8259, 1=>IOAPIC
+
+	/* The _PIC method is called by the OS to choose between interrupt
+	 * routing via the i8259 interrupt controller or the APIC.
+	 *
+	 * _PIC is called with a parameter of 0 for i8259 configuration and
+	 * with a parameter of 1 for Local Apic/IOAPIC configuration.
+	 */
+
+	Method(_PIC, 1)
+	{
+		// Remember the OS' IRQ routing choice.
+		Store(Arg0, APIC)
+	}
+
+	/* _PR CPU0 is dynamically supplied by SSDT */
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 * Any others would involve declaring the wake up methods.
+	 *
+	 * Package contents:
+	 * ofs len desc
+	 * 0   1   Value for PM1a_CNT.SLP_TYP register to enter this system state.
+	 * 1   1   Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any
+	 *         given state, OSPM must write the PM1a_CNT.SLP_TYP register before the
+	 *         PM1b_CNT.SLP_TYP register.
+	 * 2   2   Reserved
+	 */
+	Name (_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+	/* Root of the bus hierarchy */
+	Scope (_SB)
+	{
+		/* Top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00180000)
+			Name (_BBN, 0x00)
+
+			Name (APRT, Package() {
+				/* AGP? */
+				Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
+				Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
+				Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
+				/* PCIe graphics bridge */
+				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
+				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
+				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
+				/* PCIe bridge */
+				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
+				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
+				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
+				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
+				/* SATA */
+				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
+				/* IDE */
+				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
+				/* USB */
+				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
+				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
+				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
+				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
+				/* PCI bridge */
+				Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
+				Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
+				Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
+				Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
+			})
+			Name (PPRT, Package() {
+				/* ?? */
+				Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
+				Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
+				Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
+				Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
+				/* PCIe graphics bridge */
+				Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
+				Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
+				Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
+				Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
+				/* PCIe bridge */
+				Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
+				Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
+				Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
+				Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
+				/* SATA */
+				Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
+				/* USB */
+				Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
+				Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
+				Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
+				Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
+				/* PCI bridge */
+				Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
+				Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
+				Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
+				Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
+			})
+
+			/* PCI Routing Table */
+			Method (_PRT, 0, NotSerialized)
+			{
+				If (APIC)
+				{
+					Return (APRT)
+				}
+				Return (PPRT)
+			}
+
+			Device (PEGG)
+			{
+				Name (_ADR, 0x00020000)
+				Name (APRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
+				})
+				Name (PPRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
+				})
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (APIC)
+					{
+						Return (APRT)
+					}
+					Return (PPRT)
+				}
+			}
+
+			Device (PEX0)
+			{
+				Name (_ADR, 0x00030000)
+				Name (APRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
+				})
+				Name (PPRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
+				})
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (APIC)
+					{
+						Return (APRT)
+					}
+					Return (PPRT)
+				}
+			}
+
+			Device (PEX1)
+			{
+				Name (_ADR, 0x00030001)
+				Name (APRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
+				})
+				Name (PPRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
+				})
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (APIC)
+					{
+						Return (APRT)
+					}
+					Return (PPRT)
+				}
+			}
+
+			Device (PEX2)
+			{
+				Name (_ADR, 0x00030002)
+				Name (APRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
+				})
+				Name (PPRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
+					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
+				})
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (APIC)
+					{
+						Return (APRT)
+					}
+					Return (PPRT)
+				}
+			}
+
+			Device (PCI6)
+			{
+				Name (_ADR, 0x00130000)
+				Name (APRT, Package () {
+					Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
+				})
+				Name (PPRT, Package () {
+					Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 },
+				})
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (APIC)
+					{
+						Return (APRT)
+					}
+					Return (PPRT)
+				}
+			}
+
+			Device (PCI7)
+			{
+				Name (_ADR, 0x00130001)
+				Name (APRT, Package () {
+					/* PCI slot 1 */
+					Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 },
+					Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
+					Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
+					Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
+
+					/* PCI slot 2 */
+					Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 },
+					Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
+					Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
+					Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
+
+					/* PCI slot 3 */
+					Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 },
+					Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
+
+					/* PCI slot 4 */
+					Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 },
+					Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
+					Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
+					Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
+				})
+				Name (PPRT, Package () {
+					/* PCI slot 1 */
+					Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 },
+					Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
+					Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 },
+					Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
+
+					/* PCI slot 2 */
+					Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 },
+					Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 },
+					Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 },
+					Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 },
+
+					/* PCI slot 3 */
+					Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 },
+					Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 },
+					Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 },
+					Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 },
+
+					/* PCI slot 4 */
+					Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 },
+					Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 },
+					Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 },
+					Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 },
+				})
+
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (APIC)
+					{
+						Return (APRT)
+					}
+					Return (PPRT)
+				}
+			}
+
+			Device (SBRG) { /* southbridge */
+				Name (_ADR, 0x00110000)
+
+				/* PS/2 keyboard (seems to be important for WinXP install) */
+				Device (KBD)
+				{
+					Name (_HID, EisaId ("PNP0303"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+							IRQNoFlags () {1}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 mouse */
+				Device (MOU)
+				{
+					Name (_HID, EisaId ("PNP0F13"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+						     IRQNoFlags () {12}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* Parallel port */
+				Device (LPT0)
+				{
+					Name (_HID, EisaId ("PNP0401"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
+							IO (Decode16, 0x0778, 0x0778, 0x01, 0x08)
+							IRQNoFlags () {7}
+							DMA (Compatibility, NotBusMaster, Transfer8) {3}
+						})
+						Return (TMP)
+					}
+				}
+			}
+
+			External(TOM1) /* top of memory below 4GB */
+
+			Method(_CRS, 0) {
+				Name(TMP, ResourceTemplate() {
+					WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+						0x0000,             // Granularity
+						0x0000,             // Range Minimum
+						0x00FF,             // Range Maximum
+						0x0000,             // Translation Offset
+						0x0100,             // Length
+						,,
+					)
+					IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+					WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+						0x0000,			/* address granularity */
+						0x0000,			/* range minimum */
+						0x0CF7,			/* range maximum */
+						0x0000,			/* translation */
+						0x0CF8			/* length */
+					)
+
+					WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+						0x0000,			/* address granularity */
+						0x0D00,			/* range minimum */
+						0xFFFF,			/* range maximum */
+						0x0000,			/* translation */
+						0xF300			/* length */
+					)
+
+					/* memory space for PCI BARs below 4GB */
+					Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+				})
+				CreateDWordField(TMP, MMIO._BAS, MM1B)
+				CreateDWordField(TMP, MMIO._LEN, MM1L)
+				/*
+				 * Declare memory between TOM1 and 4GB as available
+				 * for PCI MMIO.
+				 *
+				 * Use ShiftLeft to avoid 64bit constant (for XP).
+				 * This will work even if the OS does 32bit arithmetic, as
+				 * 32bit (0x00000000 - TOM1) will wrap and give the same
+				 * result as 64bit (0x100000000 - TOM1).
+				 */
+				Store(TOM1, MM1B)
+				ShiftLeft(0x10000000, 4, Local0)
+				Subtract(Local0, TOM1, Local0)
+				Store(Local0, MM1L)
+
+				Return(TMP)
+			}
+		}
+
+		OperationRegion (PCI0.SBRG.SBR1, PCI_Config, 0x55, 0x03)
+		Field (PCI0.SBRG.SBR1, ByteAcc, NoLock, Preserve)
+		{
+			/*
+			 * Offset 0x55:
+			 *    3-0: reserved
+			 *    7-4: PCI INTA# routing
+			 * Offset 0x56:
+			 *    3-0: PCI INTB# routing
+			 *    7-4: PCI INTC# routing
+			 * Offset 0x57:
+			 *    3-0: reserved
+			 *    7-4: PCI INTD# routing
+			 *
+			 * Valid values for routing link:
+			 * 0:                disabled
+			 * 2,8,13:           reserved
+			 * 1,3-7,9-12,14,15: corresponding irq
+			 */
+			    , 4,
+			PINA, 4,
+			PINB, 4,
+			PINC, 4,
+			    , 4,
+			PIND, 4,
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
+		})
+
+		/* adapted from ma78gm/dsdt.asl */
+#define PCI_INTX_DEV(intx, pinx, uid)					\
+		Device(intx) {						\
+			Name(_HID, EISAID("PNP0C0F"))			\
+			Name(_UID, uid)					\
+									\
+			Method(_STA, 0) {				\
+				if (pinx) {				\
+					Return(0x0B)			\
+				}					\
+				Return(0x09)				\
+			}						\
+									\
+			Method(_DIS ,0) {				\
+				Store(0, pinx)				\
+			}						\
+									\
+			Method(_PRS ,0) {				\
+				Return(IRQP)				\
+			}						\
+									\
+			Method(_CRS ,0) {				\
+				CreateWordField(IRQB, 1, IRQN)		\
+				ShiftLeft(1, pinx, IRQN)		\
+				Return(IRQB)				\
+			}						\
+									\
+			Method(_SRS, 1) {				\
+				CreateWordField(ARG0, 1, IRQM)		\
+									\
+				/* Use lowest available IRQ */		\
+				FindSetRightBit(IRQM, Local0)		\
+				if (Local0) {				\
+					Decrement(Local0)		\
+				}					\
+				Store(Local0, pinx)			\
+			}						\
+		}							\
+
+PCI_INTX_DEV(INTA, PINA, 1)
+PCI_INTX_DEV(INTB, PINB, 2)
+PCI_INTX_DEV(INTC, PINC, 3)
+PCI_INTX_DEV(INTD, PIND, 4)
+	}
+}
Index: src/mainboard/asus/m2v/Kconfig
===================================================================
--- src/mainboard/asus/m2v/Kconfig.orig	2010-11-07 12:52:50.000000000 +0100
+++ src/mainboard/asus/m2v/Kconfig	2010-11-07 12:52:52.000000000 +0100
@@ -19,6 +19,7 @@
    select TINY_BOOTBLOCK
    select HAVE_PIRQ_TABLE
    select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES

config MAINBOARD_DIR
    string

[patch 12/16] Add M2V basic ACPI support.

[Rudolf Marek]

Add acpi tables and dsdt.

Signed-off-by: Tobias Diedrich 
Acked-by: Rudolf Marek

And commited too.

Rudolf

[patch 13/16] Add PIRQ_ROUTE support for vt8237.

[Tobias Diedrich]

The only southbridge having a pirq_assign_irqs function (needed for
CONFIG_PIRQ_ROUTE) so far is the amd cs5530.
Add one for vt8237 too.
Setting up the pci routing is important in case you want to boot DOS,
OSes that don't support ACPI or MP tables and ROMs for add-in storage
controllers may depend on this too.
TODO: Fix the 4 routing links limitation in
      src/arch/i386/boot/pirq_routing.c

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237r_pirq.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/southbridge/via/vt8237r/vt8237r_pirq.c	2010-11-07 12:59:34.000000000 +0100
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov 
+ * Copyright (C) 2010 Tobias Diedrich 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/i8259.h>
+
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char route[4])
+{
+	device_t pdev;
+
+	pdev = dev_find_device(PCI_VENDOR_ID_VIA,
+			       PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
+
+	if (pdev) {
+		pci_write_config8(pdev, 0x55,  route[0] << 4);
+		pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]);
+		pci_write_config8(pdev, 0x57,  route[3] << 4);
+
+		/* Enable INT[E-H] mapped to INT[A-D] for simplicity */
+		pci_write_config8(pdev, 0x46,  0x00);
+	}
+}
+#endif
Index: src/southbridge/via/vt8237r/Makefile.inc
===================================================================
--- src/southbridge/via/vt8237r/Makefile.inc.orig	2010-11-07 12:42:47.000000000 +0100
+++ src/southbridge/via/vt8237r/Makefile.inc	2010-11-07 12:58:53.000000000 +0100
@@ -23,5 +23,5 @@
 driver-y += vt8237r_lpc.c
 driver-y += vt8237r_sata.c
 driver-y += vt8237r_usb.c
-driver-y += vt8237r_nic.c
+driver-$(CONFIG_PIRQ_ROUTE) += vt8237r_pirq.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += vt8237_fadt.c
Index: src/mainboard/asus/m2v/Kconfig
===================================================================
--- src/mainboard/asus/m2v/Kconfig.orig	2010-11-07 12:52:52.000000000 +0100
+++ src/mainboard/asus/m2v/Kconfig	2010-11-07 12:58:53.000000000 +0100
@@ -18,6 +18,7 @@
    select RAMINIT_SYSINFO
    select TINY_BOOTBLOCK
    select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
    select HAVE_MP_TABLE
    select HAVE_ACPI_TABLES

[patch 13/16] Add PIRQ_ROUTE support for vt8237.

[Rudolf Marek]

On 7.11.2010 13:46, Tobias Diedrich wrote:
> pdev = dev_find_device(PCI_VENDOR_ID_VIA,
> 	       PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);

Can I haz S and R too please?

Thanks,
Rudolf

[patch 13/16] Add PIRQ_ROUTE support for vt8237.

[Tobias Diedrich]

Rudolf Marek wrote:
> On 7.11.2010 13:46, Tobias Diedrich wrote:
> > pdev = dev_find_device(PCI_VENDOR_ID_VIA,
> > 	       PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
>
> Can I haz S and R too please?

Sure:

Add PIRQ_ROUTE support for vt8237.

The only southbridge having a pirq_assign_irqs function (needed for
CONFIG_PIRQ_ROUTE) so far is the amd cs5530.
Add one for vt8237 too.
Setting up the pci routing is important in case you want to boot DOS,
OSes that don't support ACPI or MP tables and ROMs for add-in storage
controllers may depend on this too.
TODO: Fix the 4 routing links limitation in
      src/arch/i386/boot/pirq_routing.c

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/vt8237r/vt8237r_pirq.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ src/southbridge/via/vt8237r/vt8237r_pirq.c	2010-11-10 02:47:03.000000000 +0100
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov 
+ * Copyright (C) 2010 Tobias Diedrich 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/i8259.h>
+
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char route[4])
+{
+	device_t pdev;
+
+	pdev = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
+	if (!pdev)
+		pdev = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237S_LPC, 0);
+	if (!pdev)
+		pdev = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
+	if (!pdev)
+		return;
+
+	pci_write_config8(pdev, 0x55,  route[0] << 4);
+	pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]);
+	pci_write_config8(pdev, 0x57,  route[3] << 4);
+
+	/* Enable INT[E-H] mapped to INT[A-D] for simplicity */
+	pci_write_config8(pdev, 0x46,  0x00);
+}
+#endif
Index: src/southbridge/via/vt8237r/Makefile.inc
===================================================================
--- src/southbridge/via/vt8237r/Makefile.inc.orig	2010-11-10 02:41:11.000000000 +0100
+++ src/southbridge/via/vt8237r/Makefile.inc	2010-11-10 02:41:20.000000000 +0100
@@ -23,5 +23,5 @@
 driver-y += vt8237r_lpc.c
 driver-y += vt8237r_sata.c
 driver-y += vt8237r_usb.c
-driver-y += vt8237r_nic.c
+driver-$(CONFIG_PIRQ_ROUTE) += vt8237r_pirq.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += vt8237_fadt.c
Index: src/mainboard/asus/m2v/Kconfig
===================================================================
--- src/mainboard/asus/m2v/Kconfig.orig	2010-11-10 02:41:19.000000000 +0100
+++ src/mainboard/asus/m2v/Kconfig	2010-11-10 02:47:09.000000000 +0100
@@ -18,6 +18,7 @@
    select RAMINIT_SYSINFO
    select TINY_BOOTBLOCK
    select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
    select HAVE_ACPI_TABLES
    select HAVE_MP_TABLE

[patch 14/16] Since XP only implements parts of ACPI 2.0, it chokes on the TOM2 qword in the SSDT, which is present if a board uses k8acpi_write_vars.

[Tobias Diedrich]

This problem was introduced with
http://tracker.coreboot.org/trac/coreboot/changeset/3953

Note that all corresponding DSDTs only ever check TOM2 against 0.

Signed-off-by: Tobias Diedrich

---

Index: src/northbridge/amd/amdk8/amdk8_acpi.c
===================================================================
--- src/northbridge/amd/amdk8/amdk8_acpi.c.orig	2010-11-03 23:19:03.000000000 +0100
+++ src/northbridge/amd/amdk8/amdk8_acpi.c	2010-11-03 23:19:37.000000000 +0100
@@ -270,7 +270,15 @@
    msr = rdmsr(TOP_MEM);
    lens += acpigen_write_name_dword("TOM1", msr.lo);
    msr = rdmsr(TOP_MEM2);
-	lens += acpigen_write_name_qword("TOM2", (((uint64_t) msr.hi) << 32) | msr.lo);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);

lens += k8acpi_write_HT();
    //minus opcode
Index: src/mainboard/gigabyte/ma78gm/dsdt.asl
===================================================================
--- src/mainboard/gigabyte/ma78gm/dsdt.asl.orig	2010-11-03 23:19:03.000000000 +0100
+++ src/mainboard/gigabyte/ma78gm/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/asrock/939a785gmh/dsdt.asl
===================================================================
--- src/mainboard/asrock/939a785gmh/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/asrock/939a785gmh/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1122,7 +1122,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1530,7 +1530,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/kontron/kt690/dsdt.asl
===================================================================
--- src/mainboard/kontron/kt690/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/kontron/kt690/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/gigabyte/ma785gmt/dsdt.asl
===================================================================
--- src/mainboard/gigabyte/ma785gmt/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/gigabyte/ma785gmt/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/amd/mahogany/dsdt.asl
===================================================================
--- src/mainboard/amd/mahogany/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/mahogany/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1126,7 +1126,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1572,7 +1572,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/amd/pistachio/dsdt.asl
===================================================================
--- src/mainboard/amd/pistachio/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/pistachio/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1128,7 +1128,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1480,7 +1480,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/amd/dbm690t/dsdt.asl
===================================================================
--- src/mainboard/amd/dbm690t/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/dbm690t/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/amd/mahogany_fam10/dsdt.asl
===================================================================
--- src/mainboard/amd/mahogany_fam10/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/mahogany_fam10/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/amd/tilapia_fam10/dsdt.asl
===================================================================
--- src/mainboard/amd/tilapia_fam10/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/tilapia_fam10/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/iei/kino-780am2-fam10/dsdt.asl
===================================================================
--- src/mainboard/iei/kino-780am2-fam10/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/iei/kino-780am2-fam10/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/jetway/pa78vm5/dsdt.asl
===================================================================
--- src/mainboard/jetway/pa78vm5/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/jetway/pa78vm5/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/technexion/tim8690/dsdt.asl
===================================================================
--- src/mainboard/technexion/tim8690/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/technexion/tim8690/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/technexion/tim5690/dsdt.asl
===================================================================
--- src/mainboard/technexion/tim5690/dsdt.asl.orig	2010-11-03 23:19:29.000000000 +0100
+++ src/mainboard/technexion/tim5690/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

Index: src/mainboard/asus/m4a785-m/dsdt.asl
===================================================================
--- src/mainboard/asus/m4a785-m/dsdt.asl.orig	2010-11-03 23:19:29.000000000 +0100
+++ src/mainboard/asus/m4a785-m/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
    	/* Note: Only need HID on Primary Bus */
    	Device(PCI0) {
    		External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
    		Name(_HID, EISAID("PNP0A03"))
    		Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
    		Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
    			/*
    			* If(LNotEqual(TOM2, 0x00000000)){
    			*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
    			* }
    			*/

[patch 15/16] Query cpu instead of using CONFIG_CPU_ADDR_BITS on AMD cpus

[Tobias Diedrich]

This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the
Linux kernel, which was previously complaining that the MTRR setup
is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of
address space.

dmesg without patch:
|MTRR variable ranges enabled:
|  0 base 0000000000 mask 0F00000000 write-back
|  1 base 0100000000 mask 0FC0000000 write-back
|  2 base 00E0000000 mask 0FE0000000 uncachable
|  3 disabled
|  4 disabled
|  5 disabled
|  6 disabled
|  7 disabled
|mtrr: your BIOS has configured an incorrect mask, fixing it.

dmesg with patch:
|MTRR variable ranges enabled:
|  0 base 0000000000 mask FF00000000 write-back
|  1 base 0100000000 mask FFC0000000 write-back
|  2 base 00E0000000 mask FFE0000000 uncachable
|  3 disabled
|  4 disabled
|  5 disabled
|  6 disabled
|  7 disabled

Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c

Signed-off-by: Tobias Diedrich

---

Index: src/cpu/amd/mtrr/amd_mtrr.c
===================================================================
--- src/cpu/amd/mtrr/amd_mtrr.c	(revision 5985)
+++ src/cpu/amd/mtrr/amd_mtrr.c	(working copy)
@@ -1,5 +1,6 @@
 #include <console/console.h>
 #include <device/device.h>
+#include <arch/cpu.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/cache.h>
@@ -175,11 +176,13 @@

enable_cache();

-	/* FIXME we should probably query the cpu for this
-	 * but so far this is all any recent AMD cpu has supported.
-	 */
    address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48

+	/* AMD specific MSR to query number of address bits */
+	if (cpuid_eax(0x80000000) >= 0x80000008) {
+		address_bits = cpuid_eax(0x80000008) & 0xff;
+	}
+
    /* Now that I have mapped what is memory and what is not
     * Setup the mtrrs so we can cache the memory.
     */

[patch 15/16] Query cpu instead of usingCONFIG_CPU_ADDR_BITS on AMD cpus

[Scott Duplichan]

-----Original Message-----
From: [e-mail] [mailto:[e-mail]] On Behalf Of Tobias Diedrich
Sent: Sunday, November 07, 2010 06:47 AM
To: [e-mail]
Cc: Rudolf Marek; Tobias Diedrich
Subject: [coreboot] [patch 15/16] Query cpu instead of usingCONFIG_CPU_ADDR_BITS on AMD cpus

]This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the
]Linux kernel, which was previously complaining that the MTRR setup
]is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of
]address space.
]
]dmesg without patch:
]|MTRR variable ranges enabled:
]|  0 base 0000000000 mask 0F00000000 write-back
]|  1 base 0100000000 mask 0FC0000000 write-back
]|  2 base 00E0000000 mask 0FE0000000 uncachable
]|  3 disabled
]|  4 disabled
]|  5 disabled
]|  6 disabled
]|  7 disabled
]|mtrr: your BIOS has configured an incorrect mask, fixing it.
]
]dmesg with patch:
]|MTRR variable ranges enabled:
]|  0 base 0000000000 mask FF00000000 write-back
]|  1 base 0100000000 mask FFC0000000 write-back
]|  2 base 00E0000000 mask FFE0000000 uncachable
]|  3 disabled
]|  4 disabled
]|  5 disabled
]|  6 disabled
]|  7 disabled
]
]Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c
]
]Signed-off-by: Tobias Diedrich 
]
]---
]
]Index: src/cpu/amd/mtrr/amd_mtrr.c
]===================================================================
]--- src/cpu/amd/mtrr/amd_mtrr.c	(revision 5985)
]+++ src/cpu/amd/mtrr/amd_mtrr.c	(working copy)
]@@ -1,5 +1,6 @@
] #include <console/console.h>
] #include <device/device.h>
]+#include <arch/cpu.h>
] #include <cpu/x86/mtrr.h>
] #include <cpu/amd/mtrr.h>
] #include <cpu/x86/cache.h>
]@@ -175,11 +176,13 @@
] 
] 	enable_cache();
] 
]-	/* FIXME we should probably query the cpu for this
]-	 * but so far this is all any recent AMD cpu has supported.
]-	 */
] 	address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
] 
]+	/* AMD specific MSR to query number of address bits */
]+	if (cpuid_eax(0x80000000) >= 0x80000008) {
]+		address_bits = cpuid_eax(0x80000008) & 0xff;
]+	}
]+
] 	/* Now that I have mapped what is memory and what is not
] 	 * Setup the mtrrs so we can cache the memory.
] 	 */

Thank you Tobias. It also fixes a Win7 checked build BSOD when kconfig
CPU_ADDR_BITS is set too small. Tested with Kino-780AM2 by setting
CPU_ADDR_BITS to 36 and confirming 48 bits are set in msr 201.

Acked-by: Scott Duplichan

It looks like Intel eventually adopted this cpuid feature, though
I have no way to test the Intel implementation.

One comment could be clarified:

- /* AMD specific MSR to query number of address bits */
+ /* AMD specific cpuid function to query number of address bits */

Thanks,
Scott

[patch 15/16] Query cpu instead of usingCONFIG_CPU_ADDR_BITS on AMD cpus

[Rudolf Marek]

Committed revision 6052.

With a MSR to cpuid comment fix.

Rudolf

[patch 16/16] Ranges unavailable for PCI BARs should be marked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Tobias Diedrich]

Linux also needs the MMCONF area to be reserved either in E820 or
as an ACPI motherboard resource or it will not enable MMCONFIG
and the extended pcie configuration area will be unaccessible:

This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm not sure if the choice for the index parameter of new_resource()
is correct though.
Note that the bios rom decode is enabled in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
for the whole 4MB area (even though the comment says 1MB).

dmesg excerpt without patch:
|BIOS-provided physical RAM map:
| BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
| BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
| BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
| BIOS-e820: 0000000000100000 - 00000000dffed000 (usable)
| BIOS-e820: 00000000dffed000 - 00000000e0000000 (reserved)
| BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
[...]
|ACPI: bus type pci registered
|PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
|PCI: not using MMCONFIG
|PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=7
|PCI: Using configuration type 1 for base access
|bio: create slab <bio-0> at 0
|ACPI: EC: Look up EC in DSDT
|ACPI: Interpreter enabled
|ACPI: (supports S0 S5)
|ACPI: Using IOAPIC for interrupt routing
|PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
|[Firmware Bug]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources
|PCI: not using MMCONFIG
|PCI: DMI: pci_use_crs=1 pci_probe=0000000b
|PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
|ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
|pci_root PNP0A03:00: host bridge window [io  0x0000-0x0cf7]
|pci_root PNP0A03:00: host bridge window [io  0x0d00-0xffff]
|pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff]

dmesg excerpt with patch:
|BIOS-provided physical RAM map:
| BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
| BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
| BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
| BIOS-e820: 0000000000100000 - 00000000dffed000 (usable)
| BIOS-e820: 00000000dffed000 - 00000000f0000000 (reserved)
| BIOS-e820: 00000000fec00000 - 00000000fec00100 (reserved)
| BIOS-e820: 00000000fecc0000 - 00000000fecc0100 (reserved)
| BIOS-e820: 00000000ffc00000 - 0000000100000000 (reserved)
| BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
[...]
|ACPI: bus type pci registered
|PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
|PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
|PCI: Using MMCONFIG for extended config space
|PCI: Using configuration type 1 for base access
|bio: create slab <bio-0> at 0
|ACPI: EC: Look up EC in DSDT
|ACPI: Interpreter enabled
|ACPI: (supports S0 S5)
|ACPI: Using IOAPIC for interrupt routing
|PCI: DMI: pci_use_crs=1 pci_probe=00000008
|PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
|ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
|pci_root PNP0A03:00: host bridge window [io  0x0000-0x0cf7]
|pci_root PNP0A03:00: host bridge window [io  0x0d00-0xffff]
|pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff]

Signed-off-by: Tobias Diedrich

---

Index: src/southbridge/via/k8t890/k8t890_traf_ctrl.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_traf_ctrl.c.orig	2010-11-07 01:19:19.000000000 +0100
+++ src/southbridge/via/k8t890/k8t890_traf_ctrl.c	2010-11-07 13:23:18.000000000 +0100
@@ -58,7 +58,7 @@
    res->limit = res->base + res->size - 1;
    res->align = 8;
    res->gran = 8;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
    	     IORESOURCE_STORED | IORESOURCE_ASSIGNED;

/* Add an MMCONFIG resource. */
@@ -67,7 +67,7 @@
    res->align = log2(res->size);
    res->gran = log2(res->size);
    res->limit = 0xffffffff;	/* 4G */
-	res->flags = IORESOURCE_MEM;
+	res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
 }

static void traf_ctrl_enable_generic(struct device *dev)
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-11-07 13:00:14.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-07 13:23:18.000000000 +0100
@@ -569,7 +569,15 @@
    res->limit = 0xffffffffUL;
    res->align = 8;
    res->gran = 8;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
+		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* Fixed flashrom resource */
+	res = new_resource(dev, 4);
+	res->base = 0xffc00000UL;
+	res->size = 0x00400000UL; /* 4MB */
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
    	     IORESOURCE_STORED | IORESOURCE_ASSIGNED;

res = new_resource(dev, 1);

[patch 16/16] Ranges unavailable for PCI BARs should bemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Scott Duplichan]

-----Original Message-----
From: [e-mail] [mailto:[e-mail]] On Behalf Of Tobias Diedrich
Sent: Sunday, November 07, 2010 06:47 AM
To: [e-mail]
Cc: Rudolf Marek; Tobias Diedrich
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs should bemarked as reserved in the E820 memory map,in case the OS
wants to change the BARs.

]Linux also needs the MMCONF area to be reserved either in E820 or
]as an ACPI motherboard resource or it will not enable MMCONFIG
]and the extended pcie configuration area will be unaccessible:
]
]This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
]resource flags to do this.
]I also added a new resource for the mapped bios rom area just below 4GB.
]I'm not sure if the choice for the index parameter of new_resource()
]is correct though.
]Note that the bios rom decode is enabled in
]src/southbridge/via/vt8237r/vt8237r_early_smbus.c
]for the whole 4MB area (even though the comment says 1MB).

Thank you Tobias. To be even more conservative, the upper 5 MB of the
first 4GB can be reserved for flash memory. This is because many LPC
flash chips place the jedec ID register of the boot device at address
ffbc0000.

Thanks,
Scott

[patch 16/16] Ranges unavailable for PCI BARs should bemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Tobias Diedrich]

Scott Duplichan wrote:
> From: Tobias Diedrich
> ]Linux also needs the MMCONF area to be reserved either in E820 or
> ]as an ACPI motherboard resource or it will not enable MMCONFIG
> ]and the extended pcie configuration area will be unaccessible:
> ]
> ]This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
> ]resource flags to do this.
> ]I also added a new resource for the mapped bios rom area just below 4GB.
> ]I'm not sure if the choice for the index parameter of new_resource()
> ]is correct though.
> ]Note that the bios rom decode is enabled in
> ]src/southbridge/via/vt8237r/vt8237r_early_smbus.c
> ]for the whole 4MB area (even though the comment says 1MB).
>
> Thank you Tobias. To be even more conservative, the upper 5 MB of the
> first 4GB can be reserved for flash memory. This is because many LPC
> flash chips place the jedec ID register of the boot device at address
> ffbc0000.

I think that probably doesn't apply here, since the LPC flash
shouldn't get chip-select outside the selected area.
However src/southbridge/via/vt8237r/bootblock.c (which I had missed
because I got my board to work without touching this file)
says its actually 8MB big for VT8237A and VT8237S.

[patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Scott Duplichan]

-----Original Message-----
From: [e-mail] [mailto:[e-mail]] On Behalf Of Tobias Diedrich
Sent: Sunday, November 07, 2010 02:33 PM
To: Scott Duplichan
Cc: 'Rudolf Marek'; [e-mail]
Subject: Re: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map,in case the
OS wants to change the BARs.

]Scott Duplichan wrote:
]> From: Tobias Diedrich
]> ]Linux also needs the MMCONF area to be reserved either in E820 or
]> ]as an ACPI motherboard resource or it will not enable MMCONFIG
]> ]and the extended pcie configuration area will be unaccessible:
]> ]
]> ]This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
]> ]resource flags to do this.
]> ]I also added a new resource for the mapped bios rom area just below 4GB.
]> ]I'm not sure if the choice for the index parameter of new_resource()
]> ]is correct though.
]> ]Note that the bios rom decode is enabled in
]> ]src/southbridge/via/vt8237r/vt8237r_early_smbus.c
]> ]for the whole 4MB area (even though the comment says 1MB).
]> 
]> Thank you Tobias. To be even more conservative, the upper 5 MB of the
]> first 4GB can be reserved for flash memory. This is because many LPC
]> flash chips place the jedec ID register of the boot device at address
]> ffbc0000.
]
]I think that probably doesn't apply here, since the LPC flash
]shouldn't get chip-select outside the selected area.
]However src/southbridge/via/vt8237r/bootblock.c (which I had missed
]because I got my board to work without touching this file)
]says its actually 8MB big for VT8237A and VT8237S.

Hello Tobias,

Here is my concern,
1) Coreboot reserves only 4MB (ffc00000-ffffffff).
2) The OS then assigns a PCI memory range that ends at ffbfffff.
3) A bios flash update program is run from the OS. It expands the
   flash decode range if needed then tries to read the flash jedec
   ID at ffbc0000. Both the flash chip and PCI device are set to
   decode ffbc0000. I do not know which device wins. If the flash
   wins and overrides the PCI device, things will be OK unless the
   OS needs to access the PCI device before flashing is complete.
   If the PCI device wins and overrides the flash, then the flash
   update utility will not be able to read the jedec ID.

Thanks,
Scott

]-- 
]Tobias						PGP: http://8ef7ddba.uguu.de

[patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Rudolf Marek]

Hi,

I thought our resource allocator did not touch the high region because of 
lapic/hpet/apic stuff. Maybe it is no longer true. I got some issue with PCI 
sata  add on card (linux complaining about resource overlap on SB700)

Maybe this is heading to same direction?

Thanks,
Rudolf

[patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Scott Duplichan]

-----Original Message-----
From: Rudolf Marek [mailto:[e-mail]] 
Sent: Sunday, November 07, 2010 03:15 PM
To: Scott Duplichan
Cc: 'Tobias Diedrich'; [e-mail]
Subject: Re: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map,in case the
OS wants to change the BARs.

]Hi,
]
]I thought our resource allocator did not touch the high region because of 
]lapic/hpet/apic stuff. Maybe it is no longer true. I got some issue with PCI 
]sata  add on card (linux complaining about resource overlap on SB700)

Hello Rudolf,

You are right about coreboot, at least for the present time. However,
the allocation scheme still needs some work. For example, fec00000
and above is never allocated to a pci device because of the I/O apic,
which is on the pci bus. However, mmconf is not protected from pci use,
because it falls under 'APIC_CLUSTER: 0', and not a pci bus:
http://www.coreboot.org/pipermail/coreboot/2010-October/061320.html

I think the immediate concern for reserving flash memory space is
because the OS is allowed to make PCI resource assignments on its own.
The OS could use any range not reserved in e820. However, windows,
and possibly linux, also restrict PCI use to address ranges that ACPI
_CRS show as belonging to the pci bus. Coreboot still needs work in
this area. So maybe my example is a little far-fetched. But a commercial
BIOS reserves all the memory decoded by the flash chip, so coreboot
should probably do the same unless there is a specific reason not to.

]Maybe this is heading to same direction?

Could be. I have two overlap situations with win7 to avoid. One is the
mmconf problem described above. The other is when two video cards are
present, they both claim the legacy vga memory and I/O ranges.

]Thanks,
]Rudolf

[patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Tobias Diedrich]

Scott Duplichan wrote:
> From: Tobias Diedrich
> ]Scott Duplichan wrote:
> ]> Thank you Tobias. To be even more conservative, the upper 5 MB of the
> ]> first 4GB can be reserved for flash memory. This is because many LPC
> ]> flash chips place the jedec ID register of the boot device at address
> ]> ffbc0000.
> ]
> ]I think that probably doesn't apply here, since the LPC flash
> ]shouldn't get chip-select outside the selected area.
> ]However src/southbridge/via/vt8237r/bootblock.c (which I had missed
> ]because I got my board to work without touching this file)
> ]says its actually 8MB big for VT8237A and VT8237S.
>
> Hello Tobias,
>
> Here is my concern,
> Coreboot reserves only 4MB (ffc00000-ffffffff).
> The OS then assigns a PCI memory range that ends at ffbfffff.
> A bios flash update program is run from the OS. It expands the
> flash decode range if needed then tries to read the flash jedec
> ID at ffbc0000. Both the flash chip and PCI device are set to
> decode ffbc0000. I do not know which device wins. If the flash
> wins and overrides the PCI device, things will be OK unless the
> OS needs to access the PCI device before flashing is complete.
> If the PCI device wins and overrides the flash, then the flash
> update utility will not be able to read the jedec ID.

When coreboot reserves the full decode range (so it can't be
expanded any further) it should be fine though.

[patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map, in case the OS wants to change the BARs.

[Carl-Daniel Hailfinger]

On 08.11.2010 00:31, Tobias Diedrich wrote:
> When coreboot reserves the full decode range (so it can't be
> expanded any further) it should be fine though.

So far I have not seen flash decode ranges larger than 16 MB on any x86
chipset. Reserving less than 16 MB is very dangerous on all Intel/AMD
chipsets released in the last 6+ years because flashrom may maximize the
decode area to 16 MB after the machine has booted.

Regards,
Carl-Daniel