I'm seeing this message during boot and have made several attempts and modifying the Config.lb as the message suggests. Here's the tail of the messages:
PCI: 00:09.0 [1166/0142] disabled PCI: 00:0a.0 subbordinate bus PCI Express PCI: 00:0a.0 [1166/0144] enabled PCI: 00:0b.0 subbordinate bus PCI Express PCI: 00:0b.0 [1166/0142] disabled PCI: 00:0c.0 subbordinate bus PCI Express PCI: 00:0c.0 [1166/0144] disabled PCI: 00:01.1 PCI: Left over static devices. Check your Config.lb
I did start with a much longer list of left over devices and have narrowed it down to this one but I can't find a config that corrects the problem.
I've tried locating documentation that provides the rules for proper PCI configuration but haven't found anything that helps me understand what I've gotten wrong. Any clues I need to look for?
Thanks,
Steve
On Tue, Dec 04, 2007 at 04:08:47PM -0800, Steve Isaacs wrote:
I'm seeing this message during boot and have made several attempts and modifying the Config.lb as the message suggests. Here's the tail of the messages:
PCI: 00:09.0 [1166/0142] disabled PCI: 00:0a.0 subbordinate bus PCI Express PCI: 00:0a.0 [1166/0144] enabled PCI: 00:0b.0 subbordinate bus PCI Express PCI: 00:0b.0 [1166/0142] disabled PCI: 00:0c.0 subbordinate bus PCI Express PCI: 00:0c.0 [1166/0144] disabled PCI: 00:01.1 PCI: Left over static devices. Check your Config.lb
I did start with a much longer list of left over devices and have narrowed it down to this one but I can't find a config that corrects the problem.
I've tried locating documentation that provides the rules for proper PCI configuration but haven't found anything that helps me understand what I've gotten wrong. Any clues I need to look for?
Please post your Config.lb and 'lspci -tvnn' output.
You're likely listing PCI devices in Config.lb which are not on the board, or you use the wrong nesting or order (?)
Uwe,
On Wed, 2007-12-05 at 12:30 +0100, Uwe Hermann wrote:
Please post your Config.lb and 'lspci -tvnn' output.
You're likely listing PCI devices in Config.lb which are not on the board, or you use the wrong nesting or order (?)
Thanks, see below.
I have been in a very uncomfortable position of having to guess about this. I dug around in other boards trying to find something that almost fits and then hacked from there.
Is there anything that describes how to make a configuration in detail? I'd rather learn the rules than have someone figure it out for me.
Other questions are, in what form and how is this information used at run-time?
I apologize if I seem full of dumb or redundant questions.
Steve
Config.lb
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_F device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 off end device pci 2.0 on end device pci 3.0 off end device pci 4.0 off end end chip southbridge/broadcom/bcm11000 device pci 0.0 on end device pci 0.1 on end device pci 1.0 on device pci e.0 on end end device pci 1.1 on end device pci 2.0 on device pci b.0 on end device pci b.1 on end device pci b.2 on end device pci c.0 on end device pci c.1 on end device pci c.2 on end device pci d.0 on end device pci d.1 on end device pci d.2 on end end device pci 2.1 on end device pci 3.0 on end device pci 3.1 on end device pci 4.0 on end device pci 4.1 on end device pci 6.0 on chip drivers/i2c/i2cmux2 # pca9544 smbus mux device i2c 71 on # MIS_ P40,28,39 end #0 pca9544 0 device i2c 71 on # HT_ P40,24,42 end #0 pca9544 1 device i2c 71 on # pca9544 2 P1_ P40,2,6,7 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end end device i2c 71 on #pca9544 3 P2_ P40,8,12,13 chip drivers/generic/generic #dimm 1-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 1-1-1 device i2c 53 on end end end end end device pci 6.1 on end device pci 6.2 on chip superio/smsc/sch4304 device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 on # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.6 on # RTC io 0x60 = 0x70 io 0x62 = 0x72 end device pnp 2e.7 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end #device pnp 2e.7 off #end #device pnp 2e.B off #end end end device pci 6.3 off end device pci 6.4 on end device pci 6.5 on end device pci 6.6 on end end # bcm11000 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end #pci_domain end
$ lspci -tvnn -[0000:00]-+-01.0 1166:0031 +-02.0-[0000:01]----0f.0 1166:0410 +-03.0-[0000:02]--+-0c.0 1166:0412 | +-0c.1 1166:0412 | +-0c.2 1166:0414 | +-0d.0 1166:0412 | +-0d.1 1166:0412 | +-0d.2 1166:0414 | +-0e.0 1166:0412 | +-0e.1 1166:0412 | -0e.2 1166:0416 +-04.0-[0000:03]-- +-05.0-[0000:04]-- +-07.0 1166:0408 +-07.1 1166:0214 +-07.2 1166:040a +-08.0-[0000:05]-- +-09.0-[0000:06]-- +-0a.0-[0000:07]-- +-0b.0-[0000:08]-- +-0c.0-[0000:09]-- +-0e.0 10ec:8139 +-0f.0 1002:515e +-18.0 1022:1100 +-18.1 1022:1101 +-18.2 1022:1102 +-18.3 1022:1103 +-19.0 1022:1100 +-19.1 1022:1101 +-19.2 1022:1102 -19.3 1022:1103
On Wed, Dec 05, 2007 at 12:00:59PM -0800, Steve Isaacs wrote:
On Wed, 2007-12-05 at 12:30 +0100, Uwe Hermann wrote:
Please post your Config.lb and 'lspci -tvnn' output.
You're likely listing PCI devices in Config.lb which are not on the board, or you use the wrong nesting or order (?)
Thanks, see below.
I have been in a very uncomfortable position of having to guess about this. I dug around in other boards trying to find something that almost fits and then hacked from there.
Is there anything that describes how to make a configuration in detail? I'd rather learn the rules than have someone figure it out for me.
There's a PDF which describes some parts of it, not sure how complete it is:
$ cd documentation $ make $ xpdf LinuxBIOS-AMD64.pdf
Other questions are, in what form and how is this information used at run-time?
For the PCI parts, LinuxBIOS sets up the static/onboard devices and scans for other devices dynamically, if I'm not mistaken. This means you do not specify PCI/AGP/PCIe extention cards in Config.lb, they're rather detected at runtime.
For Super I/O stuff, the (PnP) settings are hardcoded from the options in the 'chip superio/foo/bar' section of Config.lb
The CPU/socket/APIC stuff below tells LinuxBIOS which CPU init code to execute etc.
Config.lb
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_F device apic 0 on end end end
Looks ok.
device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 off end device pci 2.0 on end device pci 3.0 off end device pci 4.0 off end end chip southbridge/broadcom/bcm11000 device pci 0.0 on end device pci 0.1 on end
Hm, not sure about the above stuff...
device pci 1.0 on device pci e.0 on end end
I may be wrong, but I don't think you can nest PCI entries like this.
device pci 1.1 on end device pci 2.0 on
device pci b.0 on end device pci b.1 on end device pci b.2 on end device pci c.0 on end device pci c.1 on end device pci c.2 on end device pci d.0 on end device pci d.1 on end device pci d.2 on end
What is 2.0? What are the b.0 etc. entries? This doesn't seem to match the lspci you posted.
end device pci 2.1 on end device pci 3.0 on end device pci 3.1 on end device pci 4.0 on end device pci 4.1 on end device pci 6.0 on chip drivers/i2c/i2cmux2 # pca9544 smbus mux device i2c 71 on # MIS_ P40,28,39 end #0 pca9544 0 device i2c 71 on # HT_ P40,24,42 end #0 pca9544 1 device i2c 71 on # pca9544 2 P1_ P40,2,6,7 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end end device i2c 71 on #pca9544 3 P2_ P40,8,12,13 chip drivers/generic/generic #dimm 1-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 1-1-1 device i2c 53 on end end end end end device pci 6.1 on end device pci 6.2 on
What device is 6.2? The Super I/O section below should be a child of the ISA/LPC device usually.
chip superio/smsc/sch4304
Please use the 'superio/smsc/smscsuperio' driver, which is a common driver for many SMSC Super I/Os. It should be easy to add support for the sch4304 there.
Do you have the sch4304 datasheet? If so, it would be nice if you could add support for this chip to superiotool, see http://linuxbios.org/Superiotool
device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 on # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.6 on # RTC io 0x60 = 0x70 io 0x62 = 0x72 end device pnp 2e.7 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end
Looks good as far as I can tell.
#device pnp 2e.7 off #end #device pnp 2e.B off #end
This section should have one entry per Super I/O LDN. If the Super I/O has some LDNs/capabilities you don't use on the board, it should still be listed, but with "off" (and a comment why it's off).
end end
device pci 6.3 off end device pci 6.4 on end device pci 6.5 on end device pci 6.6 on end
Where does this come from? I don't see 6.3, 6.4 etc. in the lspci output.
end # bcm11000 end # device pci 18.0 device pci 18.1 on end
Not sure about the above few lines. Other boards have e.g.
device pci 18.0 on end # Link 1 device pci 18.0 on end
(yes, twice, there's some reason for that which was explained in the PDF, IIRC).
device pci 18.2 on end device pci 18.3 on end
You don't have the 19.* devices from lspci listed here; not sure what those devices are, but I guess they must be listed.
end
end #pci_domain end
$ lspci -tvnn -[0000:00]-+-01.0 1166:0031 +-02.0-[0000:01]----0f.0 1166:0410 +-03.0-[0000:02]--+-0c.0 1166:0412 | +-0c.1 1166:0412 | +-0c.2 1166:0414 | +-0d.0 1166:0412 | +-0d.1 1166:0412 | +-0d.2 1166:0414 | +-0e.0 1166:0412 | +-0e.1 1166:0412 | -0e.2 1166:0416 +-04.0-[0000:03]-- +-05.0-[0000:04]-- +-07.0 1166:0408 +-07.1 1166:0214 +-07.2 1166:040a +-08.0-[0000:05]-- +-09.0-[0000:06]-- +-0a.0-[0000:07]-- +-0b.0-[0000:08]-- +-0c.0-[0000:09]-- +-0e.0 10ec:8139 +-0f.0 1002:515e +-18.0 1022:1100 +-18.1 1022:1101 +-18.2 1022:1102 +-18.3 1022:1103 +-19.0 1022:1100 +-19.1 1022:1101 +-19.2 1022:1102 -19.3 1022:1103
Can you also post the 'lspci' output? Your version of lspci doesn't attach the device names to the -tvnn output.
Thanks, Uwe.
On Dec 9, 2007 10:12 AM, Uwe Hermann uwe@hermann-uwe.de wrote:
You don't have the 19.* devices from lspci listed here; not sure what those devices are, but I guess they must be listed.
They're cpu 1 northbridge I believe.
The rule is, unless you really MUST list a device in Config.lb, don't list it.
I.e. take out most of the devices I see in this Config.lb
ron
whole boot log and your Options.lb in your MB dir ?
YH
On Sun, 2007-12-09 at 12:26 -0800, yhlu wrote:
whole boot log and your Options.lb in your MB dir ?
I just now realized that this might be what you wanted. This is the output sent to the serial port during boot.
Steve ---------
LinuxBIOS-2.0.0._apollo_Fallback OBJ-XXXX-XX Mon Dec 10 11:19:06 PST 2007 starting...
(0,1) link=01 (1,0) link=01 02 nodes initialized. core0 started: 01 01 02 03SBLink=00 NC node|link=00 SMBus controller enabled
INIT detected from ---- {APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET... (0,1) link=01 (1,0) link=03 02 nodes initialized. core0 started: 01 *01*00000001 *02*00000001 *03*00000001 SBLink=00 NC node|link=00 SMBus controller enabled ht reset - SMBus controller enabled Ram1.00 Ram1.01 Ram2.00 Registered 333Mhz Interleaved RAM: 0x00400000 KB Ram2.01 Registered 333Mhz Interleaved RAM: 0x00800000 KB Ram3 Initializing memory: done Initializing memory: done RAM: 0x00900000 KB Setting variable MTRR 02, base: 0000MB, range: 0800MB, type WB Setting variable MTRR 03, base: 0800MB, range: 0400MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=0f done DQS Training:RcvrEn:Pass1: 01 CTLRMaxDelay=12 done DQS Training:DQSPos: 00 done DQS Training:DQSPos: 01 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=41 done DQS Training:RcvrEn:Pass2: 01 CTLRMaxDelay=42 done DQS Training:tsc[00]=0000000752224b10 DQS Training:tsc[01]=00000007571fbef7 DQS Training:tsc[02]=000000075724e540 DQS Training:tsc[03]=000000087986923e DQS Training:tsc[04]=000000088462e3bf mem_trained[00]=01 mem_trained[01]=01 Ram4 v_esp=000ceef8 testx = 5a5a5a5a Copying data from cache to ram -- switching to use ram as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Copying LinuxBIOS to ram. src=fffe8000 dst=00004000 linxbios_ram.nrv2b length = 000088b7 linxbios_ram.bin length = 00017e0c Jumping to LinuxBIOS. LinuxBIOS-2.0.0._apollo_Fallback Mon Dec 10 11:19:06 PST 2007 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.3 siblings=1 CPU: APIC: 02 enabled CPU: APIC: 03 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 00:00.0 [1166/0140] enabled PCI: 00:08.0 [1166/0140] enabled next_unitid: 000d PCI: 00:00.0 [1166/0031] enabled PCI: 00:0d.0 [1166/0031] enabled next_unitid: 0015 PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [1166/0031] enabled PCI: 00:02.0 subbordinate bus PCI-X PCI: 00:02.0 [1166/0406] enabled PCI: 00:02.1 [1166/0429] enabled PCI: 00:03.0 subbordinate bus PCI-X PCI: 00:03.0 [1166/0406] enabled PCI: 00:03.1 [1166/0429] enabled PCI: 00:04.0 subbordinate bus PCI Express PCI: 00:04.0 [1166/0420] enabled PCI: 00:04.1 [1166/042a] enabled PCI: 00:05.0 subbordinate bus PCI Express PCI: 00:05.0 [1166/0422] enabled PCI: 00:05.1 [1166/042a] enabled PCI: 00:07.0 [1166/0408] enabled PCI: 00:07.1 [1166/0215] enabled PCI: 00:07.2 [1166/040a] enabled PCI: 00:07.4 [1166/040e] enabled PCI: 00:07.5 [1166/040e] enabled PCI: 00:07.6 [1166/040e] enabled PCI: 00:08.0 [1166/0140] enabled PCI: 00:09.0 subbordinate bus PCI Express PCI: 00:09.0 [1166/0142] enabled PCI: 00:0a.0 subbordinate bus PCI Express PCI: 00:0a.0 [1166/0144] enabled PCI: 00:0b.0 subbordinate bus PCI Express PCI: 00:0b.0 [1166/0142] enabled PCI: 00:0c.0 subbordinate bus PCI Express PCI: 00:0c.0 [1166/0144] enabled PCI: 00:01.1 PCI: Left over static devices. Check your Config.lb
On Sun, 2007-12-09 at 10:15 -0800, ron minnich wrote:
On Dec 9, 2007 10:12 AM, Uwe Hermann uwe@hermann-uwe.de wrote:
You don't have the 19.* devices from lspci listed here; not sure what those devices are, but I guess they must be listed.
They're cpu 1 northbridge I believe.
You're correct.
The rule is, unless you really MUST list a device in Config.lb, don't list it.
I.e. take out most of the devices I see in this Config.lb
That's something I don't understand. What is essential and what is not? e.g. Can I leave out the 18.x as well and LB will auto-detect like it did for node 1 (19.x)?
What I tried to start with is to enable only the devices that are needed to boot and leave the rest to Linux but am unsure what I need to do there.
I appreciate your helping me understand this.
Steve
On Dec 10, 2007 7:51 AM, Steve Isaacs yasteve@gmail.com wrote:
That's something I don't understand. What is essential and what is not?
Essential is "needed to configure machine to load Linux". Which really means that devices for it exist in the device tree, and those devices need to run some code to make the node boot.
e.g. Can I leave out the 18.x as well and LB will auto-detect like it did for node 1 (19.x)?
Those are northbridge register on k8 and on a 2-cpu system you need them. But do you need them in Config.lb? You know, I just realized, I don't know :-)
What I tried to start with is to enable only the devices that are needed to boot and leave the rest to Linux but am unsure what I need to do there.
Even disabled, they are still in the static tree. I am saying to not even list pci devices (particularly slots) if they are not needed to configure the platform for linuxbios. In many, many cases, all you need are the IO APIC, the superio, the CPU, and that's it. We have poor documentation and as a result people tend to put more in config.lb thany they need.
ron
On Mon, 2007-12-10 at 09:05 -0800, ron minnich wrote:
On Dec 10, 2007 7:51 AM, Steve Isaacs yasteve@gmail.com wrote:
That's something I don't understand. What is essential and what is not?
Essential is "needed to configure machine to load Linux". Which really means that devices for it exist in the device tree, and those devices need to run some code to make the node boot.
Can I assume that the list of devices needed to load Linux are a subset of devices needed to run Linux?
Just so I know I understand, let's say what I need to boot Linux is RAM and an IDE interface (on the southbridge). What I need to run Linux includes the IDE interface plus SATA, USB, (all on the southbridge)... Does Config.lb need to list these interfaces in order to run Linux or is it expected that the Linux kernel will take care of that part?
e.g. Can I leave out the 18.x as well and LB will auto-detect like it did for node 1 (19.x)?
Those are northbridge register on k8 and on a 2-cpu system you need them. But do you need them in Config.lb? You know, I just realized, I don't know :-)
Using some info in the doc Uwe reminded me of could I say that northbridge 18.* is necessary because the southbridge is connected to it? Whereas, for my board, I don't need to list northbridge 19.* because none of the "essential" devices are connected through it? (disregarding RAM of course)
Even disabled, they are still in the static tree. I am saying to not even list pci devices (particularly slots) if they are not needed to configure the platform for linuxbios. In many, many cases, all you need are the IO APIC, the superio, the CPU, and that's it. We have poor documentation and as a result people tend to put more in config.lb thany they need.
This makes me wonder about the semantics of the phrase "Left over static devices." Is this saying there are devices listed in the Config.lb that do not exist on the board or that there are devices on the board that are not mentioned in Config.lb?
Thanks to all for bearing with me on this. I need to understand this since real hardware arrives next week and is a different design.
Steve
Steve Isaacs wrote:
On Mon, 2007-12-10 at 09:05 -0800, ron minnich wrote:
e.g. Can I leave out the 18.x as well and LB will auto-detect like it did for node 1 (19.x)?
Those are northbridge register on k8 and on a 2-cpu system you need them. But do you need them in Config.lb? You know, I just realized, I don't know :-)
Using some info in the doc Uwe reminded me of could I say that northbridge 18.* is necessary because the southbridge is connected to it? Whereas, for my board, I don't need to list northbridge 19.* because none of the "essential" devices are connected through it? (disregarding RAM of course)
A devices needs to be listed in the config.lb if it requires more setup than standard PCI initialization (resource allocation). Usually that means the CPU, northbridge, southbridge, and SIO. Those devices are usually needed to indicate the system bus structure(pci_domain) as well as do any system specific initialization on those devices.
During the LinuxBIOS PCI/system scan process, if a device in config.lb is found, the functions to do customized initialization are called via the device_operations and the chip_operations structs.
Marc
On 10.12.2007 21:56, Marc Jones wrote:
A devices needs to be listed in the config.lb if it requires more setup than standard PCI initialization (resource allocation). Usually that means the CPU, northbridge, southbridge, and SIO. Those devices are usually needed to indicate the system bus structure(pci_domain) as well as do any system specific initialization on those devices.
During the LinuxBIOS PCI/system scan process, if a device in config.lb is found, the functions to do customized initialization are called via the device_operations and the chip_operations structs.
Can you add that explanation to the wiki?
Regards, Carl-Daniel
Carl-Daniel Hailfinger wrote:
On 10.12.2007 21:56, Marc Jones wrote:
A devices needs to be listed in the config.lb if it requires more setup than standard PCI initialization (resource allocation). Usually that means the CPU, northbridge, southbridge, and SIO. Those devices are usually needed to indicate the system bus structure(pci_domain) as well as do any system specific initialization on those devices.
During the LinuxBIOS PCI/system scan process, if a device in config.lb is found, the functions to do customized initialization are called via the device_operations and the chip_operations structs.
Can you add that explanation to the wiki?
Regards, Carl-Daniel
What page would this go on? I don't see an appropriate place.
Marc
On Mon, Dec 17, 2007 at 03:10:52PM -0700, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
On 10.12.2007 21:56, Marc Jones wrote:
A devices needs to be listed in the config.lb if it requires more setup than standard PCI initialization (resource allocation). Usually that means the CPU, northbridge, southbridge, and SIO. Those devices are usually needed to indicate the system bus structure(pci_domain) as well as do any system specific initialization on those devices.
During the LinuxBIOS PCI/system scan process, if a device in config.lb is found, the functions to do customized initialization are called via the device_operations and the chip_operations structs.
Can you add that explanation to the wiki?
Regards, Carl-Daniel
What page would this go on? I don't see an appropriate place.
I'd say http://linuxbios.org/Developer_Manual#Config.lb (maybe with some rewording to make it more generic and HOWTO-like)
HTH, Uwe.
Uwe Hermann wrote:
On Mon, Dec 17, 2007 at 03:10:52PM -0700, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
On 10.12.2007 21:56, Marc Jones wrote:
A devices needs to be listed in the config.lb if it requires more setup than standard PCI initialization (resource allocation). Usually that means the CPU, northbridge, southbridge, and SIO. Those devices are usually needed to indicate the system bus structure(pci_domain) as well as do any system specific initialization on those devices.
During the LinuxBIOS PCI/system scan process, if a device in config.lb is found, the functions to do customized initialization are called via the device_operations and the chip_operations structs.
Can you add that explanation to the wiki?
Regards, Carl-Daniel
What page would this go on? I don't see an appropriate place.
I'd say http://linuxbios.org/Developer_Manual#Config.lb (maybe with some rewording to make it more generic and HOWTO-like)
HTH, Uwe.
Reworded a little and added to the wiki. http://linuxbios.org/Developer_Manual#Config.lb
Marc
On 17.12.2007 23:10, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
On 10.12.2007 21:56, Marc Jones wrote:
A devices needs to be listed in the config.lb if it requires more setup than standard PCI initialization (resource allocation). Usually that means the CPU, northbridge, southbridge, and SIO. Those devices are usually needed to indicate the system bus structure(pci_domain) as well as do any system specific initialization on those devices.
During the LinuxBIOS PCI/system scan process, if a device in config.lb is found, the functions to do customized initialization are called via the device_operations and the chip_operations structs.
Can you add that explanation to the wiki?
Regards, Carl-Daniel
What page would this go on? I don't see an appropriate place.
Suggestion: Create a new page with the name "Config.lb".
Regards, Carl-Daniel
On Sun, 2007-12-09 at 19:12 +0100, Uwe Hermann wrote:
On Wed, Dec 05, 2007 at 12:00:59PM -0800, Steve Isaacs wrote:
Is there anything that describes how to make a configuration in detail? I'd rather learn the rules than have someone figure it out for me.
There's a PDF which describes some parts of it, not sure how complete it is:
$ cd documentation $ make $ xpdf LinuxBIOS-AMD64.pdf
I've seen this. It didn't appear to explain all of the Config files I was seeing but they were all new to me at the time. I'll have to revisit in case I was being dense.
For the PCI parts, LinuxBIOS sets up the static/onboard devices and scans for other devices dynamically, if I'm not mistaken. This means you do not specify PCI/AGP/PCIe extention cards in Config.lb, they're rather detected at runtime.
By "dynamic" is it meant devices for which it is possible to set the device ID (DID) in the PCI configuration space? Which means that devices for which the DID cannot be configured are considered "static"?
For Super I/O stuff, the (PnP) settings are hardcoded from the options in the 'chip superio/foo/bar' section of Config.lb
If I understand this then it is correct to have the Super I/O as a subsection under the southbridge? Oh, duh, it's there in the document you mentioned.
The CPU/socket/APIC stuff below tells LinuxBIOS which CPU init code to execute etc.
I'm really confused about which init code. I'm calling init functions in my cache_as_ram_auto.c (early functions?). btw: I've taken to calling the "early" functions "bootstrap". Is that appropriate? Is this "stage 1" in V3?
After code is copied to RAM and execution resumes in RAM are there more "init" functions? Looking at the code how do I know which is which? I've been struggling looking at nohup captured build outputs, linker commands and make files to sort this out.
Do the sections in Config.lb point to code that is executed after being copied to RAM?
device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm21000
The document shows names being appended to these (e.g. northbridge/amd/amdk8 "mc0"). What effect does that have?
device pci 1.0 on device pci e.0 on end end
I may be wrong, but I don't think you can nest PCI entries like this.
device pci 1.1 on end device pci 2.0 on
device pci b.0 on end device pci b.1 on end device pci b.2 on
What is 2.0? What are the b.0 etc. entries? This doesn't seem to match the lspci you posted.
2.0 is a PCI bridge to a number of USB devices that are on the southbridge chip.
device pci 6.2 on
What device is 6.2? The Super I/O section below should be a child of the ISA/LPC device usually.
6.2 is the LPC device on the southbridge.
chip superio/smsc/sch4304
Please use the 'superio/smsc/smscsuperio' driver, which is a common driver for many SMSC Super I/Os. It should be easy to add support for the sch4304 there.
I've seen the superio code but haven't used it because the (obsolete) snapshot of the repository which was used here before does not have it. To get started I mixed two boards, one we've already built based upon a reference design (using the AMD chipset) supported by LinuxBIOS at the time and the Broadcom Blast from the same snapshot.
Do you have the sch4304 datasheet? If so, it would be nice if you could add support for this chip to superiotool, see http://linuxbios.org/Superiotool
Yes I do. I might have an opportunity to do as you ask when the development schedule will allow more time. The snapshot I mentioned predates this.
#device pnp 2e.7 off #end #device pnp 2e.B off #end
This section should have one entry per Super I/O LDN. If the Super I/O has some LDNs/capabilities you don't use on the board, it should still be listed, but with "off" (and a comment why it's off).
This is an artifact from the config file I based this one on. I didn't delete it since I didn't understand it's purpose at the time. It didn't match the sch4304 but I need to go through the chip again to see if there is a similar device. I suspect I'll discover these are not needed and will delete them.
device pci 6.3 off end device pci 6.4 on end device pci 6.5 on end device pci 6.6 on end
Where does this come from? I don't see 6.3, 6.4 etc. in the lspci output.
This is part of my confusion. I installed a Phoenix BIOS to boot Linux and be able to run lspci. I have no visibility into what it's (Phoenix BIOS) design is for this board. I suspect there are several devices it hides (a feature of the chipset) because the assumption is they won't be needed for the reference board.
end # bcm11000 end # device pci 18.0 device pci 18.1 on end
Not sure about the above few lines. Other boards have e.g.
device pci 18.0 on end # Link 1 device pci 18.0 on end
(yes, twice, there's some reason for that which was explained in the PDF, IIRC).
I couldn't find an explanation for this in the PDF you mentioned. There is an example showing 19.0 listed three times but no comment as to why. Is this really part of hyper-transport configuration? The first for link 0, the second for link 1 and the third for link 2 (listed as LDT0, LDT1, and LDT2 in the PDF)?
You don't have the 19.* devices from lspci listed here; not sure what those devices are, but I guess they must be listed.
19.* is the second node (CPU) which may or may not be installed.
-[0000:00]-+-01.0 1166:0031 +-02.0-[0000:01]----0f.0 1166:0410 +-03.0-[0000:02]--+-0c.0 1166:0412 | +-0c.1 1166:0412 | +-0c.2 1166:0414 | +-0d.0 1166:0412 | +-0d.1 1166:0412 | +-0d.2 1166:0414 | +-0e.0 1166:0412 | +-0e.1 1166:0412 | -0e.2 1166:0416 +-04.0-[0000:03]-- +-05.0-[0000:04]-- +-07.0 1166:0408 +-07.1 1166:0214 +-07.2 1166:040a +-08.0-[0000:05]-- +-09.0-[0000:06]-- +-0a.0-[0000:07]-- +-0b.0-[0000:08]-- +-0c.0-[0000:09]-- +-0e.0 10ec:8139 +-0f.0 1002:515e +-18.0 1022:1100 +-18.1 1022:1101 +-18.2 1022:1102 +-18.3 1022:1103 +-19.0 1022:1100 +-19.1 1022:1101 +-19.2 1022:1102 -19.3 1022:1103
Can you also post the 'lspci' output? Your version of lspci doesn't attach the device names to the -tvnn output.
One thing that keeps tripping me is it appears that some device numbers are 0 based and others are 1 based. For example 18.0 agrees with a PCI bus scan as well as 19.0 but 6.0 in the Config shows up as 7.0 in the scan and 0.0 as 1.0. What's up with that? Is there a rule I need to understand? On the surface this seems very inconsistent.
Here's a portion of my Options.lb that might be relevant.
#HT Unit ID offset default HT_CHAIN_UNITID_BASE=0x08
#real SB Unit ID default HT_CHAIN_END_UNITID_BASE=0x1
#make the SB HT chain on bus 0 default SB_HT_CHAIN_ON_BUS0=1
Here's the output you requested. I've included the output from print_pci_devices() (debug.c).
Thanks,
Steve
---------
$ lspci 00:01.0 Host bridge: Broadcom Unknown device 0031 (rev a0) 00:02.0 PCI bridge: Broadcom Unknown device 0406 (rev a0) 00:03.0 PCI bridge: Broadcom Unknown device 0406 (rev a0) 00:04.0 PCI bridge: Broadcom Unknown device 0420 (rev a0) 00:05.0 PCI bridge: Broadcom Unknown device 0422 (rev a0) 00:07.0 Host bridge: Broadcom Unknown device 0408 00:07.1 IDE interface: Broadcom HT1000 Legacy IDE controller (rev a0) 00:07.2 ISA bridge: Broadcom Unknown device 040a 00:08.0 PCI bridge: Broadcom Unknown device 0140 (rev a2) 00:09.0 PCI bridge: Broadcom Unknown device 0142 (rev a2) 00:0a.0 PCI bridge: Broadcom Unknown device 0144 (rev a2) 00:0b.0 PCI bridge: Broadcom Unknown device 0142 (rev a2) 00:0c.0 PCI bridge: Broadcom Unknown device 0144 (rev a2) 00:0f.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:0f.0 RAID bus controller: Broadcom Unknown device 0410 02:0c.0 USB Controller: Broadcom Unknown device 0412 (rev a0) 02:0c.1 USB Controller: Broadcom Unknown device 0412 (rev a0) 02:0c.2 USB Controller: Broadcom Unknown device 0414 (rev a0) 02:0d.0 USB Controller: Broadcom Unknown device 0412 (rev a0) 02:0d.1 USB Controller: Broadcom Unknown device 0412 (rev a0) 02:0d.2 USB Controller: Broadcom Unknown device 0414 (rev a0) 02:0e.0 USB Controller: Broadcom Unknown device 0412 (rev a0) 02:0e.1 USB Controller: Broadcom Unknown device 0412 (rev a0) 02:0e.2 USB Controller: Broadcom Unknown device 0416 (rev a0)
Output from print_pci_devices() (running using cache as ram).
PCI: 00:01.00 0x1166 0x0031 PCI: 00:01.01 0x1166 0x0428 PCI: 00:02.00 0x1166 0x0406 PCI: 00:02.01 0x1166 0x0429 PCI: 00:03.00 0x1166 0x0406 PCI: 00:03.01 0x1166 0x0429 PCI: 00:04.00 0x1166 0x0420 PCI: 00:04.01 0x1166 0x042a PCI: 00:05.00 0x1166 0x0422 PCI: 00:05.01 0x1166 0x042a PCI: 00:07.00 0x1166 0x0408 PCI: 00:07.01 0x1166 0x0215 PCI: 00:07.02 0x1166 0x040a PCI: 00:07.04 0x1166 0x040e PCI: 00:07.05 0x1166 0x040e PCI: 00:07.06 0x1166 0x040e PCI: 00:0f.00 0x1002 0x515e PCI: 00:0f.01 0x1002 0x515e PCI: 00:0f.02 0x1002 0x515e PCI: 00:0f.03 0x1002 0x515e PCI: 00:0f.04 0x1002 0x515e PCI: 00:0f.05 0x1002 0x515e PCI: 00:0f.06 0x1002 0x515e PCI: 00:0f.07 0x1002 0x515e PCI: 00:10.00 0x1166 0x0140 PCI: 00:11.00 0x1166 0x0142 PCI: 00:12.00 0x1166 0x0144 PCI: 00:13.00 0x1166 0x0142 PCI: 00:14.00 0x1166 0x0144 PCI: 00:18.00 0x1022 0x1100 PCI: 00:18.01 0x1022 0x1101 PCI: 00:18.02 0x1022 0x1102 PCI: 00:18.03 0x1022 0x1103 PCI: 00:19.00 0x1022 0x1100 PCI: 00:19.01 0x1022 0x1101 PCI: 00:19.02 0x1022 0x1102 PCI: 00:19.03 0x1022 0x1103
On Mon, Dec 10, 2007 at 10:08:30AM -0800, Steve Isaacs wrote:
For the PCI parts, LinuxBIOS sets up the static/onboard devices and scans for other devices dynamically, if I'm not mistaken. This means you do not specify PCI/AGP/PCIe extention cards in Config.lb, they're rather detected at runtime.
By "dynamic" is it meant devices for which it is possible to set the device ID (DID) in the PCI configuration space? Which means that devices for which the DID cannot be configured are considered "static"?
No, I don't think this has anything to do with the DID. But I'm not really an expert here, better listen to Ron (see other mail).
For Super I/O stuff, the (PnP) settings are hardcoded from the options in the 'chip superio/foo/bar' section of Config.lb
If I understand this then it is correct to have the Super I/O as a subsection under the southbridge?
Yes.
Do the sections in Config.lb point to code that is executed
Sort of, yes. E.g. the keywords "io" and "irq" etc. in the Super I/O section are "translated" to function calls in src/device/pnp_device.c and others. PCI entries are translated into function calls in src/device/*pci*.c.
device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm21000
The document shows names being appended to these (e.g. northbridge/amd/amdk8 "mc0"). What effect does that have?
None. It's just a comment for humans to better understand the file.
device pci 6.2 on
What device is 6.2? The Super I/O section below should be a child of the ISA/LPC device usually.
6.2 is the LPC device on the southbridge.
OK, good, that's correct then.
Do you have the sch4304 datasheet? If so, it would be nice if you could add support for this chip to superiotool, see http://linuxbios.org/Superiotool
Yes I do. I might have an opportunity to do as you ask when the development schedule will allow more time.
Great, thanks.
Where does this come from? I don't see 6.3, 6.4 etc. in the lspci output.
This is part of my confusion. I installed a Phoenix BIOS to boot Linux and be able to run lspci. I have no visibility into what it's (Phoenix BIOS) design is for this board. I suspect there are several devices it hides (a feature of the chipset) because the assumption is they won't be needed for the reference board.
Hm, not sure. I usually use lspci from the vendor BIOS (Phoenix in your case) for comparison purposes. Yes, some devices may not appear (some depend on the BIOS config menu settings; e.g. the menu may allow to enable/disable an AC97 modem or not, etc), but the majority of devices (and their IDs) should be correct.
Can you also post the 'lspci' output? Your version of lspci doesn't attach the device names to the -tvnn output.
One thing that keeps tripping me is it appears that some device numbers are 0 based and others are 1 based. For example 18.0 agrees with a PCI bus scan as well as 19.0 but 6.0 in the Config shows up as 7.0 in the scan and 0.0 as 1.0. What's up with that?
Hm, good question. Someone else will have to answer it.
Here's the output you requested. I've included the output from print_pci_devices() (debug.c).
Please also post the lspci from the vendor BIOS for comparison.
Thanks, Uwe.
On Mon, 2007-12-10 at 21:25 +0100, Uwe Hermann wrote:
On Mon, Dec 10, 2007 at 10:08:30AM -0800, Steve Isaacs wrote:
One thing that keeps tripping me is it appears that some device numbers are 0 based and others are 1 based. For example 18.0 agrees with a PCI bus scan as well as 19.0 but 6.0 in the Config shows up as 7.0 in the scan and 0.0 as 1.0. What's up with that?
Hm, good question. Someone else will have to answer it.
Thanks to you're reminding me of Stefan Reinauer's PDF I might be able to take a stab at it. The key sentence from the "pci" section is: "The first occurrence of the pci keyword tells LinuxBIOS where the bridge devices start, [and this is the key part] relative to the PCI configuration space used by the bridge." So, in my case the ht1100 starts at DID 1 (let's call that bridge DID or DIDb) and devices are enumerated as DIDb + 0, DIDb + 1 and so on. If I look at it that way I can deduce when 0 is needed. Does that seem correct?
Here's the output you requested. I've included the output from print_pci_devices() (debug.c).
Please also post the lspci from the vendor BIOS for comparison.
I did post the Phoenix BIOS since I'm currently unable to boot using LinuxBIOS.
Steve
On Dec 10, 2007 10:08 AM, Steve Isaacs yasteve@gmail.com wrote:
This is part of my confusion. I installed a Phoenix BIOS to boot Linux and be able to run lspci. I have no visibility into what it's (Phoenix BIOS) design is for this board. I suspect there are several devices it hides (a feature of the chipset) because the assumption is they won't be needed for the reference board.
once again. You probably don't need a lot of those "pci 6.0 on" bits. yank them out.
Your board is not working, and the best thing you can do is shrink down Config.lb until it works.
You need the ioapic, the 18. devices, and the superio. try starting there.
device pci 18.0 on end # Link 1 device pci 18.0 on end
each 18. device connects to three HT channels. There's no real way to express this in PCI, so we got stuck with the three instances.
You need 3 19. devices since the 19. bits (CPU1) are configured from CPU0 and they each have 3 HT links.
I couldn't find an explanation for this in the PDF you mentioned. There is an example showing 19.0 listed three times but no comment as to why. Is this really part of hyper-transport configuration? The first for link 0, the second for link 1 and the third for link 2 (listed as LDT0, LDT1, and LDT2 in the PDF)?
that's it!
One thing that keeps tripping me is it appears that some device numbers are 0 based and others are 1 based. For example 18.0 agrees with a PCI bus scan as well as 19.0 but 6.0 in the Config shows up as 7.0 in the scan and 0.0 as 1.0. What's up with that? Is there a rule I need to understand? On the surface this seems very inconsistent.
The rule is that difference bios'es will order busses differently. hence the weirdness. Shrink the config.lb to start.
ron
On Dec 10, 2007 1:19 PM, ron minnich rminnich@gmail.com wrote:
On Dec 10, 2007 10:08 AM, Steve Isaacs yasteve@gmail.com wrote:
This is part of my confusion. I installed a Phoenix BIOS to boot Linux and be able to run lspci. I have no visibility into what it's (Phoenix BIOS) design is for this board. I suspect there are several devices it hides (a feature of the chipset) because the assumption is they won't be needed for the reference board.
once again. You probably don't need a lot of those "pci 6.0 on" bits. yank them out.
Your board is not working, and the best thing you can do is shrink down Config.lb until it works.
You need the ioapic, the 18. devices, and the superio. try starting there.
device pci 18.0 on end # Link 1 device pci 18.0 on end
each 18. device connects to three HT channels. There's no real way to express this in PCI, so we got stuck with the three instances.
You need 3 19. devices since the 19. bits (CPU1) are configured from CPU0 and they each have 3 HT links.
No, you don't need that. I have made it automatically detect that. So you only need the chain that down to superio. if my memory is right, the auto detect is in northbridge.c
YH
On Dec 10, 2007 1:39 PM, yhlu yinghailu@gmail.com wrote:
No, you don't need that. I have made it automatically detect that. So you only need the chain that down to superio. if my memory is right, the auto detect is in northbridge.c
oops, forgot you had done that!
So, what should his Config look like?
ron
On Dec 10, 2007 1:51 PM, ron minnich rminnich@gmail.com wrote:
On Dec 10, 2007 1:39 PM, yhlu yinghailu@gmail.com wrote:
No, you don't need that. I have made it automatically detect that. So you only need the chain that down to superio. if my memory is right, the auto detect is in northbridge.c
oops, forgot you had done that!
So, what should his Config look like?
northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_F device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 on end device pci 2.0 on end device pci 3.0 on end device pci 4.0 on end end chip southbridge/broadcom/bcm11000 device pci 0.0 on end device pci 1.0 on end device pci 1.1 on end device pci 2.0 on end device pci 2.1 on end device pci 3.0 on end device pci 3.1 on end device pci 4.0 on end device pci 4.1 on end device pci 6.0 on end device pci 6.1 on end device pci 6.2 on chip superio/smsc/sch4304 device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 on # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.6 on # RTC io 0x60 = 0x70 io 0x62 = 0x72 end device pnp 2e.7 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end #device pnp 2e.7 off #end #device pnp 2e.B off #end end end device pci 6.3 off end device pci 6.4 on end device pci 6.5 on end device pci 6.6 on end end # bcm11000 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end #pci_domain end
On Dec 10, 2007 2:52 PM, yhlu yinghailu@gmail.com wrote:
On Dec 10, 2007 1:51 PM, ron minnich rminnich@gmail.com wrote:
On Dec 10, 2007 1:39 PM, yhlu yinghailu@gmail.com wrote:
No, you don't need that. I have made it automatically detect that. So you only need the chain that down to superio. if my memory is right, the auto detect is in northbridge.c
oops, forgot you had done that!
So, what should his Config look like?
northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_F device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0
OK
chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 on end device pci 2.0 on end device pci 3.0 on end device pci 4.0 on end end
why do we need all of these?
chip southbridge/broadcom/bcm11000 device pci 0.0 on end device pci 1.0 on end device pci 1.1 on end device pci 2.0 on end device pci 2.1 on end device pci 3.0 on end device pci 3.1 on end device pci 4.0 on end device pci 4.1 on end device pci 6.0 on end device pci 6.1 on end device pci 6.2 on
Why do we need all of these?
chip superio/smsc/sch4304 device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 on # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.6 on # RTC io 0x60 = 0x70 io 0x62 = 0x72 end device pnp 2e.7 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end #device pnp 2e.7 off #end #device pnp 2e.B off #end end end
device pci 6.3 off end device pci 6.4 on end device pci 6.5 on end device pci 6.6 on end
why do we need these?
end # bcm11000 end # device pci 18.0
device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end
do we need these or are they auto discovered
thanks
ron
On Dec 10, 2007 3:03 PM, ron minnich rminnich@gmail.com wrote:
On Dec 10, 2007 2:52 PM, yhlu yinghailu@gmail.com wrote:
On Dec 10, 2007 1:51 PM, ron minnich rminnich@gmail.com wrote:
On Dec 10, 2007 1:39 PM, yhlu yinghailu@gmail.com wrote:
No, you don't need that. I have made it automatically detect that. So you only need the chain that down to superio. if my memory is right, the auto detect is in northbridge.c
oops, forgot you had done that!
So, what should his Config look like?
northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_F device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0
OK
chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 on end device pci 2.0 on end device pci 3.0 on end device pci 4.0 on end end
why do we need all of these?
chip southbridge/broadcom/bcm11000 device pci 0.0 on end device pci 1.0 on end device pci 1.1 on end device pci 2.0 on end device pci 2.1 on end device pci 3.0 on end device pci 3.1 on end device pci 4.0 on end device pci 4.1 on end device pci 6.0 on end device pci 6.1 on end device pci 6.2 on
Why do we need all of these?
chip superio/smsc/sch4304 device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 on # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.6 on # RTC io 0x60 = 0x70 io 0x62 = 0x72 end device pnp 2e.7 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end #device pnp 2e.7 off #end #device pnp 2e.B off #end end end
device pci 6.3 off end device pci 6.4 on end device pci 6.5 on end device pci 6.6 on end
why do we need these?
end # bcm11000 end # device pci 18.0
device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end
do we need these or are they auto discovered
you could remove them. but in case you may need to set it to off to disable some devices ... if sb code support that.
YH
I tried this config and it got this far (hangs after second SOFT_RESET):
LinuxBIOS-2.0.0._apollo_Fallback OBJ-XXXX-XX Mon Dec 10 15:21:11 PST 2007 starting...
(0,1) link=01 (1,0) link=01 02 nodes initialized. core0 started: 01 01 02 03SBLink=00 NC node|link=00 SMBus controller enabled
INIT detected from ---- {APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET... (0,1) link=01 (1,0) link=03 02 nodes initialized. core0 started: 01 *01*00000001 *02*00000001 *03*00000001 SBLink=00 NC node|link=00 SMBus controller enabled ht reset - SMBus controller enabled Ram1.00 Ram1.01 Ram2.00 Registered 333Mhz Interleaved RAM: 0x00400000 KB Ram2.01 Registered 333Mhz Interleaved RAM: 0x00800000 KB Ram3 Initializing memory: done Initializing memory: done RAM: 0x00900000 KB Setting variable MTRR 02, base: 0000MB, range: 0800MB, type WB Setting variable MTRR 03, base: 0800MB, range: 0400MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=78 done DQS Training:RcvrEn:Pass1: 01 CTLRMaxDelay=12 done DQS Training:DQSPos: 00 done DQS Training:DQSPos: 01 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=79 done DQS Training:RcvrEn:Pass2: 01 CTLRMaxDelay=43 done DQS Training:tsc[00]=000000071b69c5bc DQS Training:tsc[01]=0000000723387656 DQS Training:tsc[02]=00000007233d3693 DQS Training:tsc[03]=000000081d5816f9 DQS Training:tsc[04]=0000000826dc49ca mem_trained[00]=01 mem_trained[01]=01 Ram4 v_esp=000ceef8 testx = 5a5a5a5a Copying data from cache to ram -- switching to use ram as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region:
INIT detected from ---- {APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
On Mon, 2007-12-10 at 14:52 -0800, yhlu wrote:
northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_F device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 on end device pci 2.0 on end device pci 3.0 on end device pci 4.0 on end end chip southbridge/broadcom/bcm11000 device pci 0.0 on end device pci 1.0 on end device pci 1.1 on end device pci 2.0 on end device pci 2.1 on end device pci 3.0 on end device pci 3.1 on end device pci 4.0 on end device pci 4.1 on end device pci 6.0 on end device pci 6.1 on end device pci 6.2 on chip superio/smsc/sch4304 device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 on # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.6 on # RTC io 0x60 = 0x70 io 0x62 = 0x72 end device pnp 2e.7 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end #device pnp 2e.7 off #end #device pnp 2e.B off #end end end device pci 6.3 off end device pci 6.4 on end device pci 6.5 on end device pci 6.6 on end end # bcm11000 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end #pci_domain end
Steve Isaacs wrote:
I tried this config and it got this far (hangs after second SOFT_RESET):
LinuxBIOS-2.0.0._apollo_Fallback OBJ-XXXX-XX Mon Dec 10 15:21:11 PST 2007 starting...
...
Ram1.00 Ram1.01 Ram2.00 Registered 333Mhz Interleaved RAM: 0x00400000 KB Ram2.01 Registered 333Mhz Interleaved RAM: 0x00800000 KB Ram3 Initializing memory: done Initializing memory: done RAM: 0x00900000 KB Setting variable MTRR 02, base: 0000MB, range: 0800MB, type WB Setting variable MTRR 03, base: 0800MB, range: 0400MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=78 done DQS Training:RcvrEn:Pass1: 01 CTLRMaxDelay=12 done DQS Training:DQSPos: 00 done DQS Training:DQSPos: 01 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=79 done DQS Training:RcvrEn:Pass2: 01 CTLRMaxDelay=43 done DQS Training:tsc[00]=000000071b69c5bc DQS Training:tsc[01]=0000000723387656 DQS Training:tsc[02]=00000007233d3693 DQS Training:tsc[03]=000000081d5816f9 DQS Training:tsc[04]=0000000826dc49ca mem_trained[00]=01 mem_trained[01]=01 Ram4 v_esp=000ceef8 testx = 5a5a5a5a Copying data from cache to ram -- switching to use ram as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region:
INIT detected from ---- {APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
When I have seen a soft reset at this point it has been due to a memory problem. Try simpler configurations and try putting some basic memory test just before CAR is disabled. I would try on the interesting boundaries. For example, check where LinuxBIOS gets copied at 2MB and across a dimm boundary like 1GB+2MB.
ram_check(0x00200000, 0x00200000 + (640 * 1024)); ram_check(0x40200000, 0x40200000 + (640 * 1024));
Also, most of the memory registers are located in Function 2 if you decide to dump and compare them.
Marc
On Mon, 2007-12-10 at 17:32 -0700, Marc Jones wrote:
Steve Isaacs wrote:
INIT detected from ---- {APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
When I have seen a soft reset at this point it has been due to a memory problem. Try simpler configurations and try putting some basic memory test just before CAR is disabled. I would try on the interesting boundaries. For example, check where LinuxBIOS gets copied at 2MB and across a dimm boundary like 1GB+2MB.
ram_check(0x00200000, 0x00200000 + (640 * 1024)); ram_check(0x40200000, 0x40200000 + (640 * 1024));
Also, most of the memory registers are located in Function 2 if you decide to dump and compare them.
Thanks, I'll give it a try. So, it may be that this problem is masking a correct config?
It might be tomorrow or the next day before I have a result. I've got meetings and a doc to finish.
Steve
On Mon, 2007-12-10 at 17:32 -0700, Marc Jones wrote:
When I have seen a soft reset at this point it has been due to a memory problem. Try simpler configurations and try putting some basic memory test just before CAR is disabled. I would try on the interesting boundaries. For example, check where LinuxBIOS gets copied at 2MB and across a dimm boundary like 1GB+2MB.
ram_check(0x00200000, 0x00200000 + (640 * 1024)); ram_check(0x40200000, 0x40200000 + (640 * 1024));
Also, most of the memory registers are located in Function 2 if you decide to dump and compare them.
Thanks, so far I'm not seeing any anomalies with RAM. I've peeked and poked RAM at a number of boundaries with no apparent problems.
A clue I've encountered is that the device 00:01.1 is there in the PCI bus scan during CAR and absent after CAR at the time of the pci bus scan (pci_scan_bus). There is a "feature" in the southbridge regarding this I don't yet understand. I have to put my forensic glasses back on...
btw: based upon this information I've deduced that if a device is listed in the Config.lb but does not appear in the bus scan it is identified as a "Left over device." Is this correct?
I'm thinking that an experiment which might prove interesting is to temporarily change pci_scan_bus to not die when this device is "Left over..." and see where that gets me.
Steve
On Dec 12, 2007 11:05 AM, Steve Isaacs yasteve@gmail.com wrote:
btw: based upon this information I've deduced that if a device is listed in the Config.lb but does not appear in the bus scan it is identified as a "Left over device." Is this correct?
yes.
I'm thinking that an experiment which might prove interesting is to temporarily change pci_scan_bus to not die when this device is "Left over..." and see where that gets me.
sure, it can't hurt ...
ron
ron minnich wrote:
On Dec 12, 2007 11:05 AM, Steve Isaacs yasteve@gmail.com wrote:
I'm thinking that an experiment which might prove interesting is to temporarily change pci_scan_bus to not die when this device is "Left over..." and see where that gets me.
sure, it can't hurt ...
Should it die if a a device isn't found? Seems like that would be a warning. I can imagine some cases where a device might or might not be installed on a mainboard that could be supported by a single ROM image.
Marc
On Dec 12, 2007 11:19 AM, Marc Jones marc.jones@amd.com wrote:
Should it die if a a device isn't found? Seems like that would be a warning. I can imagine some cases where a device might or might not be installed on a mainboard that could be supported by a single ROM image.
I thought the same way at first. I figured a leftover device could be safely ignored. But it gets a little complicated. How do you know whether it is safe to ignore it or not? In many cases, you really don't.
There should really be limited device enumeration in Config.lb. Only those devices needed to be touched by LB should be listed. I still think that the Config.lb that was listed in this thread is over-specifying the hardware.
Given this rule, left-over devices should really not be allowed, because, it means that you listed devices LB is supposed to do something with and then did not specify how to do something with them.
put another way, a device listed in LB should not be optional. If a device is optional, it should not be in Config.lb. (I think).
thanks
ron
On Wed, 2007-12-12 at 11:15 -0800, ron minnich wrote:
On Dec 12, 2007 11:05 AM, Steve Isaacs yasteve@gmail.com wrote:
I'm thinking that an experiment which might prove interesting is to temporarily change pci_scan_bus to not die when this device is "Left over..." and see where that gets me.
sure, it can't hurt ...
This got me a lot further with another issue that points back to RAM (as Marc suspects).
CI: 01: 133MHz PCI-X PCI: pci_scan_bus for bus 02 PCI: 02:0c.0 [1166/0412] enabled PCI: 02:0c.1 [1166/0412] enabled PCI: 02:0c.2 [1166/0414] enabled PCI: 02:0d.0 [1166/0412] enabled PCI: 02:0d.1 [1166/0412] enabled PCI: 02:0d.2 [1166/0414] enabled Error! malloc: free_mem_ptr >= free_mem_end_ptr
The 0412 and 0414 devices are the USB devices I'd expect to see. This is good!
So, this gives me something else to look at (starting with _eheap) and an open question as to why the southbridge is hiding the 00:01.1 device (my problem I believe).
Thanks everyone for all the suggestions and help.
Steve
On Mon, 2007-12-10 at 13:19 -0800, ron minnich wrote:
Your board is not working, and the best thing you can do is shrink down Config.lb until it works.
I performed a series of experiments stripping the Config.lb none of which fixed my issue. The process I followed was to comment out devices one at a time and see what the effect was. If a device had others nested I commented out those as well. The results I observed either ran or hung. If commenting a device caused a hang I power cycled the board and tried again to verify that the result was repeatable -- all failures were. I then un-commented the same device and repeated to verify that the restoring the device in the config would run. If restoring the device would run I then labeled the device as essential and moved to the next in the list. Below I've included the results produced using this method.
I'm thinking that stripping to the essential is a good thing but since it didn't correct my problem I'm wondering if it might be an incorrectly nested device.
You need the ioapic, the 18. devices, and the superio. try starting there.
device pci 18.0 on end # Link 1 device pci 18.0 on end
each 18. device connects to three HT channels. There's no real way to express this in PCI, so we got stuck with the three instances.
Something I learned is that in my case I need two 18.0s. The board I'm using has nothing connected to link2 so I'm suspecting including a third 18.0 would hang the boot.
btw: I just now received YH's suggestions so will try that to see what happens.
Here's the resulting config with the commented sections included:
device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm21000 # HT2100 VID=0x1166 device pci 0.0 on # EXB0 DID=0x0140 end device pci 1.0 off # EXB1 DID=0x0142 end device pci 2.0 on # EXB2 DID=0x0144 end device pci 3.0 off # EXB3 DID=0x0142 end device pci 4.0 off # EXB4 DID=0x0144 end end chip southbridge/broadcom/bcm11000 # HT1000 device pci 0.0 on end device pci 0.1 on end # device pci 1.0 on # device pci e.0 on # end # end # device pci 1.1 on # end # device pci 2.0 on # device pci b.0 on # end # device pci b.1 on # end # device pci b.2 on # end # device pci c.0 on # end # device pci c.1 on # end # device pci c.2 on # end # device pci d.0 on # end # device pci d.1 on # end # device pci d.2 on # end # end device pci 2.1 on end device pci 3.0 on end device pci 3.1 on end # device pci 4.0 on # end # device pci 4.1 on # end device pci 6.0 on chip drivers/i2c/i2cmux2 # pca9544 smbus mux device i2c 71 on # MIS_ P40,28,39 end #0 pca9544 0 device i2c 71 on # HT_ P40,24,42 end #0 pca9544 1 device i2c 71 on # pca9544 2 P1_ P40,2,6,7 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end end device i2c 71 on #pca9544 3 P2_ P40,8,12,13 chip drivers/generic/generic #dimm 1-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 1-1-1 device i2c 53 on end end end end end device pci 6.1 on end device pci 6.2 on chip superio/smsc/sch4304 device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 on # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.6 on # RTC io 0x60 = 0x70 io 0x62 = 0x72 end device pnp 2e.7 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end end end # device pci 6.3 off # end # device pci 6.4 on # end # device pci 6.5 on # end # device pci 6.6 on # end end # bcm11000 end # device pci 18.0 device pci 18.0 on # Link 1 end # device pci 18.0 on # Link 2 # end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end #pci_domain
Steve Isaacs wrote:
chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 off end device pci 2.0 on end device pci 3.0 off end device pci 4.0 off end end
Your HT2100 part looks ok. Here is what I have used successfully on a 2100 board:
chip southbridge/broadcom/bcm21000 # HT2100 device pci 0.0 on end # PCIe 0 device pci 1.0 on end # PCIe 1 device pci 2.0 on end # PCIe 2 device pci 3.0 on end # PCIe 3 device pci 4.0 on end # PCIe 4 end
My board has all 5 PCIe ports in use, so they are all enabled. From your "offs", it looks like you must be using the x16/x8 mux option, but that seems to conflict with below:
$ lspci -tvnn -[0000:00]-+-01.0 1166:0031 +-02.0-[0000:01]----0f.0 1166:0410 +-03.0-[0000:02]--+-0c.0 1166:0412 | +-0c.1 1166:0412 | +-0c.2 1166:0414 | +-0d.0 1166:0412 | +-0d.1 1166:0412 | +-0d.2 1166:0414 | +-0e.0 1166:0412 | +-0e.1 1166:0412 | -0e.2 1166:0416 +-04.0-[0000:03]-- +-05.0-[0000:04]-- +-07.0 1166:0408 +-07.1 1166:0214 +-07.2 1166:040a +-08.0-[0000:05]-- +-09.0-[0000:06]-- +-0a.0-[0000:07]-- +-0b.0-[0000:08]-- +-0c.0-[0000:09]-- +-0e.0 10ec:8139 +-0f.0 1002:515e +-18.0 1022:1100 +-18.1 1022:1101 +-18.2 1022:1102 +-18.3 1022:1103 +-19.0 1022:1100 +-19.1 1022:1101 +-19.2 1022:1102 -19.3 1022:1103
Where are the HT2100 PCIe controllers? I would expect to see 1166:0140 or 142 or 144.
I would suggest that you turn them all "on" as an experiment. The Config.lb tree description has always been confusing, with documentation that doesn't talk much about new chipsets. The only way I ever got anything to work was by trial and error. (and my LB complains about leftover statics on my board if I turn any of the HT2100 ports "off")
I can't really give you any comments on the HT1100 stuff, since I have not seen that databook.
On Sun, 2007-12-09 at 15:56 -0500, Tom Sylla wrote:
Steve Isaacs wrote:
chip southbridge/broadcom/bcm21000 device pci 0.0 on end device pci 1.0 off end device pci 2.0 on end device pci 3.0 off end device pci 4.0 off end end
Your HT2100 part looks ok. Here is what I have used successfully on a 2100 board:
chip southbridge/broadcom/bcm21000 # HT2100 device pci 0.0 on end # PCIe 0 device pci 1.0 on end # PCIe 1 device pci 2.0 on end # PCIe 2 device pci 3.0 on end # PCIe 3 device pci 4.0 on end # PCIe 4 end
My board has all 5 PCIe ports in use, so they are all enabled. From your "offs", it looks like you must be using the x16/x8 mux option, but that seems to conflict with below:
Yes, it's x16/x8.
Where are the HT2100 PCIe controllers? I would expect to see 1166:0140 or 142 or 144.
I would suggest that you turn them all "on" as an experiment. The Config.lb tree description has always been confusing, with documentation that doesn't talk much about new chipsets. The only way I ever got anything to work was by trial and error. (and my LB complains about leftover statics on my board if I turn any of the HT2100 ports "off")
I'm not sure how much of the lspci output can be believed since it was produced using a Phoenix BIOS on the board (since I don't have a LinuxBIOS config that will boot yet). Also, I don't believe I can perform the experiment you request since I don't have control of the BIOS that was used to capture the lspci output.
Steve