Patch set updated for coreboot: ee068e8 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.

[Marc Jones]

Marc Jones ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/627

-gerrit

commit ee068e84d951b1d198007371d767b920e82ba149
Author: Marc Jones 
Date:   Mon Jan 30 19:30:45 2012 -0700

Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.

The MTRR check for WB TOM2 setting was only checking revF, not extended family
    revisions. All families above revf indicate 0xf in the family field and have
    additional bits in the extended family field.

Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
    Signed-off-by: Marc Jones 
---
 src/cpu/amd/mtrr/amd_mtrr.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index c5e01b1..54a70e2 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -114,12 +114,13 @@ void amd_setup_mtrrs(void)
    msr_t msr, sys_cfg;
    // Test if this CPU is a Fam 0Fh rev. F or later
    const int cpu_id = cpuid_eax(0x80000001);
+	printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id);
    const int has_tom2wb =
-		 (((cpu_id>>8 )&0xf)  > 0xf) || // Family > 0F
+		 (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0
    	((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
    	 (((cpu_id>>16)&0xf) >= 0x4));  // Rev>=F deduced from rev tables
    if(has_tom2wb)
-		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB\n");
+		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");

/* Enable the access to AMD RdDram and WrDram extension bits */
    disable_cache();