Re: [coreboot] Coreboot and Kabylake FSP-M

[roman perepelitsin]

Here coreboot log.
Also I'm using next values for FSP-M config:

*DqPinsInterleaved = FALSE;*
* CaVrefConfig = 2; *
* RefClk = 0;*
* RcompResistor[3] = { 121, 121, 100 };*
* RcompTarget[5] = { 120, 34, 39, 39, 39 };*

*/* Debug set - UART0 115200 -  all the same  -** didn't work** */*
*PcdDebugInterfaceFlags = 1 << 1;PcdSerialIoUartNumber =
0;PcdIsaSerialUartBase = 0;PcdSerialDebugBaudRate = 7;PcdSerialDebugLevel =
5;*

About RcompTarget - I didn't find fully describe of this values, only this
- "RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv". So, what
means cmd/ctl/clk DRV?

пт, 30 нояб. 2018 г. в 00:53, Naresh G. Solanki <
[e-mail]>:
> It mostly looks like fspm parameters are incorrect for memory init.
> Can you please attach coreboot logs?
>
> Regards,
> Naresh G Solanki
>
> On Fri 30 Nov, 2018, 2:50 AM roman perepelitsin <
> [e-mail] wrote:
> > Hi!
> > I'm try to run Coreboot on Intel Xeon1505L with C236 and DDR4 memory down
> > using kabylake FSP GOLD. I setup UART0 for coreboot console out and try to
> > set UART0 for FSP-M debug out, but have only POST codes to port80/81 from
> > FSP-M. In FSP integration guide I didn't find full POST-codes describe.
> > So - can some body help with this? My lasts post codes: DD46h DD30h DD32h
> > DD35h DD45h DD36h DD37h DD41h DD4Dh DD3fh. I think it MRC codes, but that
> > they mean - don't know. I see in oscilloscope, that DDR try to start in
> > this stage, but after all I have error from FSP-M 80000007h.