Hi all,
I am a newbie, and trying to understand RAM / DRAM initialization code. I have understood upto SMBus Controller / I2C protocol and how it can be used to get SPD information from DRAM module (DDR/DDR2/DD3/...).
After that I get stuck completely mainly because of RAM initialization steps as per JEDEC. I am looking for resources or tutorials which can point to me in right direction as to how read SPD info and use that to configure or initialize RAM module.
Your help will definitely help me in understanding very core of RAM initialization process. My sole purpose is to enhance my knowledge.
I also don't know if I am allowed to post such queries or if this mailing list is only for advanced level users.
Regards Mohit Gupta
Am 26.08.2013 09:12, schrieb Mohit Gupta:
After that I get stuck completely mainly because of RAM initialization steps as per JEDEC. I am looking for resources or tutorials which can point to me in right direction as to how read SPD info and use that to configure or initialize RAM module.
Memory initialization varies a lot by the standard (DDR2 vs DDR3, for example), and - when looking at it from the point of view of a firmware implementer - also by the chipset that drives the memory. For example the VIA chipsets with DDR3 support seem to do many things by itself that must be handled explicitely by initialization code on other chipsets.
I find our RAM init code for older Intel chipsets quite readable. But I'm probably biased because I was part of the development teams for that code.
You can find it at src/northbridge/i945 (driving DDR2) and src/northbridge/gm45 (DDR3) in our source tree. http://www.coreboot.org/Git describes how to access the source code.
I also don't know if I am allowed to post such queries or if this mailing list is only for advanced level users.
There are no requirements for participating in the coreboot community beyond common courtesy. Given the rather special topic we cover it helps to be curious in the lower levels of computer technology (and coreboot development in particular, but there are many people here whose interests are on a tangent to that), and it helps to be willing to research topics autonomously to some degree since this is a community of volunteers.
Regards, Patrick
On Mon, Aug 26, 2013 at 1:13 AM, Patrick Georgi patrick@georgi-clan.dewrote:
Am 26.08.2013 09:12, schrieb Mohit Gupta:
After that I get stuck completely mainly because of RAM initialization steps as per JEDEC. I am looking for resources or tutorials which can point to me in right direction as to how read SPD info and use that to configure or initialize RAM module.
Memory initialization varies a lot by the standard (DDR2 vs DDR3, for example), and - when looking at it from the point of view of a firmware implementer - also by the chipset that drives the memory. For example the VIA chipsets with DDR3 support seem to do many things by itself that must be handled explicitely by initialization code on other chipsets.
I find our RAM init code for older Intel chipsets quite readable. But I'm probably biased because I was part of the development teams for that code.
You can find it at src/northbridge/i945 (driving DDR2) and src/northbridge/gm45 (DDR3) in our source tree. http://www.coreboot.org/Git describes how to access the source code.
As Patrick pointed out, it is quite specific to the hardware you are working on. And unfortunately documentation is scarce. Fortunately AMD publishes a good deal of info about their DRAM controller init in their BIOS and Kernel Developer's Guides (BKDG). Section 2.9.7 of the Family 16h BKDG sheds some light on the steps involved: http://developer.amd.com/resources/documentation-articles/developer-guides-m...
In addition to the resources Patrick pointed out, you can also find DDR3 memory controller init code for Exynos5-series processors. The code for the Exynos5420 currently lives in the coreboot repo on chromium.org and is not too hairy: http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=blob...
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David Hendricks -
Mohit Gupta -
Patrick Georgi