Preview: SECC Pentium 2/3 users are gonna love this

[Keith Hui]

See this boot log: http://coreboot.pastebin.com/rdmwwvha

I have done the 72oz steak ;-P that is porting the L2 enabling code
from coreboot v1 to current trunk, made much slimmer by being able to
put it post-raminit.

The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache.
Tell me if I am headed the right direction.

Patch to come soonish.

Enjoy
Keith

PS. Oh by the way...

[root@ojisan ~]# cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Pentium III (Katmai)
stepping        : 3
cpu MHz         : 601.352
cache size      : 512 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca
cmov pse36 mmx fxsr sse up
bogomips        : 1202.70
clflush size    : 32
power management:

[root@ojisan ~]#

[Joseph Smith]

On Tue, 11 May 2010 21:53:29 -0400, Keith Hui  wrote:
> See this boot log: http://coreboot.pastebin.com/rdmwwvha
>
> I have done the 72oz steak ;-P that is porting the L2 enabling code
> from coreboot v1 to current trunk, made much slimmer by being able to
> put it post-raminit.
>
> The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache.
> Tell me if I am headed the right direction.
>
> Patch to come soonish.
>
> Enjoy
> Keith
>
> PS. Oh by the way...
>
> [root@ojisan ~]# cat /proc/cpuinfo
> processor       : 0
> vendor_id       : GenuineIntel
> cpu family      : 6
> model           : 7
> model name      : Pentium III (Katmai)
> stepping        : 3
> cpu MHz         : 601.352
> cache size      : 512 KB
> fdiv_bug        : no
> hlt_bug         : no
> f00f_bug        : no
> coma_bug        : no
> fpu             : yes
> fpu_exception   : yes
> cpuid level     : 2
> wp              : yes
> flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca
> cmov pse36 mmx fxsr sse up
> bogomips        : 1202.70
> clflush size    : 32
> power management:
>
> [root@ojisan ~]#

Congrats! :-)

One question, your bootlog says the cache is only 128k ?

[Keith Hui]

Yes, the debug output from the L2 init code does say 128K, but
/proc/cpuinfo reports 512K. This is where I'd like some expert
opinions.

Thanks
Keith

On Wed, May 12, 2010 at 7:18 AM, Joseph Smith  wrote:
> On Tue, 11 May 2010 21:53:29 -0400, Keith Hui  wrote:
> > See this boot log: http://coreboot.pastebin.com/rdmwwvha
> >
> > I have done the 72oz steak ;-P that is porting the L2 enabling code
> > from coreboot v1 to current trunk, made much slimmer by being able to
> > put it post-raminit.
> >
> > The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache.
> > Tell me if I am headed the right direction.
> >
> > Patch to come soonish.
> >
> > Enjoy
> > Keith
> >
> > PS. Oh by the way...
> >
> > [root@ojisan ~]# cat /proc/cpuinfo
> > processor       : 0
> > vendor_id       : GenuineIntel
> > cpu family      : 6
> > model           : 7
> > model name      : Pentium III (Katmai)
> > stepping        : 3
> > cpu MHz         : 601.352
> > cache size      : 512 KB
> > fdiv_bug        : no
> > hlt_bug         : no
> > f00f_bug        : no
> > coma_bug        : no
> > fpu             : yes
> > fpu_exception   : yes
> > cpuid level     : 2
> > wp              : yes
> > flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca
> > cmov pse36 mmx fxsr sse up
> > bogomips        : 1202.70
> > clflush size    : 32
> > power management:
> >
> > [root@ojisan ~]#
>
> Congrats! :-)
>
> One question, your bootlog says the cache is only 128k ?

[Joseph Smith]

On Wed, 12 May 2010 11:48:57 -0400, Keith Hui  wrote:
> Yes, the debug output from the L2 init code does say 128K, but
> /proc/cpuinfo reports 512K. This is where I'd like some expert
> opinions.

Sure, but we need to see the code to give an opinion :-)