Re: [coreboot] Gsoc 12

[Marc Jones]

Hi Jaspal,

Welcome to coreboot.

On Fri, Mar 9, 2012 at 11:54 AM, Jaspal Dhillon  wrote:
> Hello ,
>
> I am currently a 4th year student ( B.Tech in CSE + MS ) in IIIT-H and
> chosen field of study for MS is Virtualization. I have been using kvm , qemu
> and the libvirt library primarily to experiment with cloud frameworks and
> migration until now.
>
> I was going through the coreboot.org and I am definitely interested in it.
> So wanted to ask couple of things.
> I have not read the source code yet but tried it out in this way :
> 1.Checked out latest version of coreboot on 32bit Fedora 15. make config
> with settings as :
> MainBoard Vendor : Emulation , Model : Qemu , ROM Size : 256KB , Payload :
> SeaBIOS
> make was successful .
> Since my laptop is an old one and does not have hardware virtualization
> support , I use a lab pc ( 64 bit Fedora 15 ) for some of my experiments.
>
> scp coreboot.rom root@Lab: ; ssh root@Lab
> 2.qemu-img create disk.img 2500M
> 3.mkfs.ext2 disk.img
> 4.mkdir foo ; mv coreboot.rom foo/ ; cd foo ; ln -s coreboot.rom bios.bin
> 5.Copy some of the other bios files needed by Qemu ( otherwise , Qemu throws
> a file not found error and exits ):
> cp -r
> qemu_path/pc-bios/{keymaps,kvmapic.bin,pxe-e1000.rom,vgabios-cirrus.bin}
> /root/foo/
> 6.qemu-system-x86_64 -L foo/ -hda disk.img -vnc 0:0 -m 512 -serial stdio
> -cdrom ~/CentOS-5.5-i386-bin-DVD.iso
>
> Installation of CentOS ( Minimum installation ) was successful and at the
> end , it asked me to reboot. When I clicked on reboot option , coreboot got
> stuck in an infinite loop and I was getting this (in a loop) on the stdio :
>
> Changing serial settings was 0/0 now 3/0
> In resume (status=0)
> In 32bit resume
> Attempting a hard reboot
>
> I killed the process and started my vm again without the -cdrom option and
> it booted up fine.
> I am not sure if this is a bug or if I am doing something wrong. Can you
> shed light on it ?

I am not sure why the -cdrom issue is needed. it may be a seabios or qemu issue.
> I have pasted the serial output at the end of email. ( There are some other
> 'file not found' errors but qemu + coreboot worked fine without them ).
>
> I am absolutely new to coreboot and used it for the first time today but I
> love and admire it's goal , to replace the proprietary BIOS. Always thought
> , where's the code of BIOS ?
> Could you give me some pointers as to where to begin for GSoC or some little
> hacks that I should attempt out ? I am trying different payloads in the
> meantime.
> The initrd and vmlinuz of the CentOS I just installed have sizes of 3.2MB
> and 1.8MB respectively. If I want to use them ( a kernel payload ) , how
> should I ? I read about mkelfImage command and also tried it out but the
> resultant size of linux.elf is ~5MB which exceeds the size of ROM chip ,
> declared in Qemu. Can I use a kernel payload ( any other OS ) without
> hacking Qemu ? ( I think not but want to know , if yes , how ) .

It sounds like you did this correctly and that the .elf is the correct
size. You will need to increase the rom size in qemu. I'm not sure how
it is done. Maybe someone else can answer?
> Thanks ,
> Jaspal

Please join the #coreboot IRC channel. Then we can try to help you as
you are working on these problems.

Regards,
Marc
> The complete serial log :
>
> [root@divecloud2 jaspal]# qemu-system-x86_64 -L foo/ -hda disk.img -m 512
> -serial stdio -vnc 0:0 -cdrom ~/CentOS-5.5-i386-bin-DVD.iso
> Could not open option rom 'vapic.bin': No such file or directory
> qemu-system-x86_64: pci_add_option_rom: failed to find romfile
> "pxe-rtl8139.rom"
>
> coreboot-4.0-2087-gc5fc7db Fri Mar  9 04:04:49 IST 2012 starting...
> Loading image.
> Searching for fallback/coreboot_ram
> Check cmos_layout.bin
> Check fallback/romstage
> Check fallback/coreboot_ram
> Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @
> 0x100000
> Stage: done loading.
> Jumping to image.
> coreboot-4.0-2087-gc5fc7db Fri Mar  9 04:04:49 IST 2012 booting...
> Enumerating buses...
> Show all devs...Before device enumeration.
> Root Device: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> Compare with tree...
> Root Device: enabled 1
>  PCI_DOMAIN: 0000: enabled 1
>   PCI: 00:00.0: enabled 1
>   PCI: 00:01.0: enabled 1
>   PCI: 00:01.1: enabled 1
> scan_static_bus for Root Device
> Finding PCI configuration type.
> PCI: Using configuration type 1
> PCI_DOMAIN: 0000 enabled
> PCI_DOMAIN: 0000 scanning...
> PCI: pci_scan_bus for bus 00
> PCI: 00:00.0 [8086/1237] ops
> PCI: 00:00.0 [8086/1237] enabled
> PCI: 00:01.0 [8086/7000] bus ops
> PCI: 00:01.0 [8086/7000] enabled
> PCI: 00:01.1 [8086/7010] ops
> PCI: 00:01.1 [8086/7010] enabled
> PCI: 00:01.3 [8086/7113] bus ops
> pwrmgt_enable: gpo default missing in devicetree.cb!
> PCI: 00:01.3 [8086/7113] enabled
> PCI: 00:02.0 [1013/00b8] ops
> PCI: 00:02.0 [1013/00b8] enabled
> PCI: 00:03.0 [10ec/8139] enabled
> scan_static_bus for PCI: 00:01.0
> scan_static_bus for PCI: 00:01.0 done
> scan_static_bus for PCI: 00:01.3
> scan_static_bus for PCI: 00:01.3 done
> PCI: pci_scan_bus returning with max=000
> scan_static_bus for Root Device done
> done
> Setting up VGA for PCI: 00:02.0
> Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
> Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
> Allocating resources...
> Reading resources...
> Root Device read_resources bus 0 link: 0
> PCI_DOMAIN: 0000 read_resources bus 0 link: 0
> PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
> Root Device read_resources bus 0 link: 0 done
> Done reading resources.
> Show resources in subtree (Root Device)...After reading.
>  Root Device child on link 0 PCI_DOMAIN: 0000
>   PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
>   PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
> 40040100 index 10000000
>   PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
> flags 40040200 index 10000100
>   PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit
> ffffffff flags e0000200 index 2
>   PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit
> ffffffff flags e0000200 index 3
>    PCI: 00:00.0
>    PCI: 00:01.0
>    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags
> c0000100 index 1
>    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0
> flags d0000200 index 2
>    PCI: 00:01.1
>    PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
> index 20
>    PCI: 00:01.3
>    PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags
> d0000100 index 1
>    PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags
> d0000100 index 2
>    PCI: 00:02.0
>    PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff
> flags 1200 index 10
>    PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
> flags 200 index 14
>    PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff
> flags 2200 index 30
>    PCI: 00:03.0
>    PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100
> index 10
>    PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
> 200 index 14
> PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
> limit: ffff
> PCI: 00:03.0 10 *  [0x0 - 0xff] io
> PCI: 00:01.1 20 *  [0x400 - 0x40f] io
> PCI_DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0
> limit: ffff done
> PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
> limit: ffffffff
> PCI: 00:02.0 10 *  [0x0 - 0x1ffffff] prefmem
> PCI: 00:02.0 30 *  [0x2000000 - 0x200ffff] mem
> PCI: 00:02.0 14 *  [0x2010000 - 0x2010fff] mem
> PCI: 00:03.0 14 *  [0x2011000 - 0x20110ff] mem
> PCI_DOMAIN: 0000 compute_resources_mem: base: 2011100 size: 2011100 align:
> 25 gran: 0 limit: ffffffff done
> avoid_fixed_resources: PCI_DOMAIN: 0000
> avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
> avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
> constrain_resources: PCI_DOMAIN: 0000
> constrain_resources: PCI: 00:00.0
> constrain_resources: PCI: 00:01.0
> constrain_resources: PCI: 00:01.1
> constrain_resources: PCI: 00:01.3
> constrain_resources: PCI: 00:02.0
> constrain_resources: PCI: 00:03.0
> avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
>     lim->base 00001000 lim->limit 0000e3ff
> avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
>     lim->base 00000000 lim->limit febfffff
> Setting resources...
> PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0
> limit:e3ff
> Assigned: PCI: 00:03.0 10 *  [0x1000 - 0x10ff] io
> Assigned: PCI: 00:01.1 20 *  [0x1400 - 0x140f] io
> PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8
> gran: 0 done
> PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2011100 align:25
> gran:0 limit:febfffff
> Assigned: PCI: 00:02.0 10 *  [0xfc000000 - 0xfdffffff] prefmem
> Assigned: PCI: 00:02.0 30 *  [0xfe000000 - 0xfe00ffff] mem
> Assigned: PCI: 00:02.0 14 *  [0xfe010000 - 0xfe010fff] mem
> Assigned: PCI: 00:03.0 14 *  [0xfe011000 - 0xfe0110ff] mem
> PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 2011100
> align: 25 gran: 0 done
> Root Device assign_resources, bus 0 link: 0
> Detected 524288 Kbytes (512 MiB) RAM.
> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
> PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04
> io
> PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19
> prefmem
> PCI: 00:02.0 14 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c
> mem
> PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10
> romem
> PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08
> io
> PCI: 00:03.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08
> mem
> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
> Root Device assign_resources, bus 0 link: 0
> Done setting resources.
> Show resources in subtree (Root Device)...After assigning values.
>  Root Device child on link 0 PCI_DOMAIN: 0000
>   PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
>   PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff
> flags 40040100 index 10000000
>   PCI_DOMAIN: 0000 resource base fc000000 size 2011100 align 25 gran 0 limit
> febfffff flags 40040200 index 10000100
>   PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit
> ffffffff flags e0000200 index 2
>   PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit
> ffffffff flags e0000200 index 3
>   PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
> e0004200 index a
>   PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0
> flags e0004200 index b
>    PCI: 00:00.0
>    PCI: 00:01.0
>    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags
> c0000100 index 1
>    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0
> flags d0000200 index 2
>    PCI: 00:01.1
>    PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags
> 60000100 index 20
>    PCI: 00:01.3
>    PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags
> d0000100 index 1
>    PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags
> d0000100 index 2
>    PCI: 00:02.0
>    PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit
> febfffff flags 60001200 index 10
>    PCI: 00:02.0 resource base fe010000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 14
>    PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit
> febfffff flags 60002200 index 30
>    PCI: 00:03.0
>    PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags
> 60000100 index 10
>    PCI: 00:03.0 resource base fe011000 size 100 align 8 gran 8 limit
> febfffff flags 60000200 index 14
> Done allocating resources.
> Enabling resources...
> PCI: 00:00.0 cmd <- 00
> PCI: 00:01.0 cmd <- 00
> PCI: 00:01.1 cmd <- 01
> PCI: 00:01.3 cmd <- 00
> PCI: 00:02.0 cmd <- 03
> PCI: 00:03.0 cmd <- 03
> done.
> Initializing devices...
> Root Device init
> PCI: 00:00.0 init
> Keyboard init...
> setting ethernet
> Assigning IRQ 11 to 0:3.0
> i8259_configure_irq_trigger: current interrupts are 0x0
> i8259_configure_irq_trigger: try to set interrupts 0x800
> PCI: 00:01.0 init
> RTC Init
> PCI: 00:01.1 init
> IDE: Primary IDE interface: on
> IDE: Secondary IDE interface: on
> IDE: Access to legacy IDE ports: off
> PCI: 00:02.0 init
> Searching for pci1013,00b8.rom
> Check cmos_layout.bin
> Check fallback/romstage
> Check fallback/coreboot_ram
> Check fallback/payload
> Check config
> Check
> Could not find file 'pci1013,00b8.rom'.
> On card, ROM address for PCI: 00:02.0 = fe000000
> PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038
> PCI ROM image, vendor ID 1013, device ID 00b8,
> PCI ROM image, Class Code 030000, Code Type 00
> Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes
> Real mode stub @00000600: 862 bytes
> Calling Option ROM...
> ... Option ROM returned.
> PCI: 00:03.0 init
> Searching for pci10ec,8139.rom
> Check cmos_layout.bin
> Check fallback/romstage
> Check fallback/coreboot_ram
> Check fallback/payload
> Check config
> Check
> Could not find file 'pci10ec,8139.rom'.
> Devices initialized
> Show all devs...After init.
> Root Device: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:01.3: enabled 1
> PCI: 00:02.0: enabled 1
> PCI: 00:03.0: enabled 1
> Initializing CBMEM area to 0x1fff0000 (65536 bytes)
> Adding CBMEM entry as no. 1
> Moving GDT to 1fff0200...ok
> High Tables Base is 1fff0000.
> Copying Interrupt Routing Table to 0x000f0000... done.
> Adding CBMEM entry as no. 2
> Copying Interrupt Routing Table to 0x1fff0400... done.
> PIRQ table: 128 bytes.
> Adding CBMEM entry as no. 3
> smbios_write_tables: 1fff1400
> Root Device (QEMU Mainboard)
> PCI_DOMAIN: 0000 (QEMU Northbridge)
> PCI: 00:00.0 (QEMU Northbridge)
> PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
> PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
> PCI: 00:01.3 ()
> PCI: 00:02.0 ()
> PCI: 00:03.0 ()
> SMBIOS tables: 357 bytes.
> Adding CBMEM entry as no. 4
> Writing high table forward entry at 0x00000500
> Wrote coreboot table at: 00000500 - 00000518  checksum c3df
> New low_table_end: 0x00000518
> Now going to write high coreboot table at 0x1fff1c00
> rom_table_end = 0x1fff1c00
> Adjust low_table_end from 0x00000518 to 0x00001000
> Adjust rom_table_end from 0x1fff1c00 to 0x20000000
> Adding high table area
> coreboot memory table:
>  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
>  1. 0000000000001000-000000000009ffff: RAM
>  2. 00000000000c0000-000000001ffeffff: RAM
>  3. 000000001fff0000-000000001fffffff: CONFIGURATION TABLES
>  4. 00000000ff800000-00000000ffffffff: RESERVED
> Wrote coreboot table at: 1fff1c00 - 1fff1dd0  checksum fe3d
> coreboot table: 464 bytes.
> Multiboot Information structure has been written.
>  0. FREE SPACE 1fff3c00 0000c400
>  1. GDT        1fff0200 00000200
>  2. IRQ TABLE  1fff0400 00001000
>  3. SMBIOS     1fff1400 00000800
>  4. COREBOOT   1fff1c00 00002000
> Searching for fallback/payload
> Check cmos_layout.bin
> Check fallback/romstage
> Check fallback/coreboot_ram
> Check fallback/payload
> Got a payload
> Loading segment from rom address 0xfffc99b8
>   code (compression=1)
>   New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfffc99f0 filesize
> 0xc21c
>   (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfffc99f0
> filesize 0xc21c
> Loading segment from rom address 0xfffc99d4
>   Entry Point 0x00000000
> Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz:
> 0x000000000000c21c
> lb: [0x0000000000100000, 0x0000000000124000)
> Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz:
> 0x000000000000c21c
> using LZMA
> [ 0x000e7e04, 00100000, 0x00100000) <- fffc99f0
> dest 000e7e04, end 00100000, bouncebuffer 1ffa8000
> Loaded segments
> Jumping to boot code at fc8b9
> entry    = 0x000fc8b9
> lb_start = 0x00100000
> lb_size  = 0x00024000
> adjust   = 0x1fecc000
> buffer   = 0x1ffa8000
>      elf_boot_notes = 0x00110538
> adjusted_boot_notes = 0x1ffdc538
> Start bios (version 1.6.3-20120309_040510-redevil)
> Found mainboard Emulation QEMU x86
> Found CBFS header at 0xfffffc90
> Ram Size=0x1fff0000 (0x0000000000000000 high)
> Relocating init from 0x000e8450 to 0x1ffd57a0 (size 42812)
> CPU Mhz=2936
> Found 6 PCI devices (max PCI bus is 00)
> Found 1 cpu(s) max supported 1 cpu(s)
> Copying PIR from 0x1fff0400 to 0x000fdb70
> Copying SMBIOS entry point from 0x1fff1400 to 0x000fdb50
> Scan for VGA option rom
> Running option rom at c000:0003
> Turning on vga text mode console
> SeaBIOS (version 1.6.3-20120309_040510-redevil)
>
> Found 1 lpt ports
> Found 1 serial ports
> ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9)
> ATA controller 2 at 170/374/0 (irq 15 dev 9)
> ata0-0: QEMU HARDDISK ATA-7 Hard-Disk (2500 MiBytes)
> Searching bootorder for: /pci@i0cf8/*@1,1/drive@0/disk@0
> DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD]
> Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0
> PS2 keyboard initialized
> All threads complete.
> Scan for option roms
> Press F12 for boot menu.
>
> drive 0x000fdb00: PCHS=5079/16/63 translation=large LCHS=634/128/63
> s=5120000
> ebda moved from 9fc00 to 9f400
> Returned 65536 bytes of ZoneHigh
> e820 map has 6 items:
>   0: 0000000000000000 - 000000000009f400 = 1 RAM
>   1: 000000000009f400 - 00000000000a0000 = 2 RESERVED
>   2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
>   3: 0000000000100000 - 000000001fff0000 = 1 RAM
>   4: 000000001fff0000 - 0000000020000000 = 2 RESERVED
>   5: 00000000ff800000 - 0000000100000000 = 2 RESERVED
> enter handle_19:
>   NULL
> Booting from DVD/CD...
> 3991MB medium detected
> Booting from 0000:7c00
> Changing serial settings was 0/0 now 3/0
> In resume (status=0)
> In 32bit resume
> Attempting a hard reboot
> Changing serial settings was 0/0 now 3/0
> In resume (status=0)
> In 32bit resume
> Attempting a hard reboot
> Changing serial settings was 0/0 now 3/0
> In resume (status=0)
> In 32bit resume
> Attempting a hard reboot
> Changing serial settings was 0/0 now 3/0
> In resume (status=0)
> In 32bit resume
> Attempting a hard reboot