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On 05/25/2017 12:35 PM, BogDan Vatra wrote:
Hi,
It's this a false positive? i.e. it's a problem with the test or actually coreboot doesn't boot?
BogDan.
There remains an undiagnosed race condition in coreboot's Opteron startup code that leads to an occasional (empirically this seems to be a 1 in 3 chance) hang in ramstage when the debug level is cranked up and the AP console output is enabled.
I've been wondering if I should lower the debug level on the test stand for this particular board to mask the problem, or if these occasional reminders might prod someone to take a look at the problem?
- -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com
On Thu, May 25, 2017 at 11:58 AM, Timothy Pearson tpearson@raptorengineering.com wrote: ...
It's this a false positive? i.e. it's a problem with the test or actually coreboot doesn't boot?
...
I've been wondering if I should lower the debug level on the test stand for this particular board to mask the problem, or if these occasional reminders might prod someone to take a look at the problem?
My opinion is that you should lower the debug level if that solves the problem. Having REACTS fail occasionally for a known bug on that platform probably won't spur anyone to look at that problem, it will just make people ignore real failures.
Martin
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Martin Roth -
Timothy Pearson