New Defects reported by Coverity Scan for coreboot

Hi,

Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

1 new defect(s) introduced to coreboot found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)

** CID 1501549:  Control flow issues  (DEADCODE)
/src/soc/amd/morgana/fch.c: 154 in gpp_clk_setup()

________________________________________________________________________________________________________
*** CID 1501549:  Control flow issues  (DEADCODE)
/src/soc/amd/morgana/fch.c: 154 in gpp_clk_setup()
148     		 * devicetree settings is the clock being enabled, so that a missing devicetree
149     		 * configuration for this will result in an always active clock and not an
150     		 * inactive PCIe clock output. Only the configuration for the clock outputs
151     		 * available on the package is provided via the devicetree; the rest is
152     		 * switched off unconditionally.
153     		 */
> > > CID 1501549:  Control flow issues  (DEADCODE)
> > > Execution cannot reach the expression "GPP_CLK_OFF" inside this statement: "switch ((i < 7) ? cfg->gpp_...".

154     		switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) {
155     		case GPP_CLK_REQ:
156     			gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
157     			break;
158     		case GPP_CLK_OFF:
159     			gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);

________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P0...