Author: uwe Date: 2009-06-07 16:38:32 +0200 (Sun, 07 Jun 2009) New Revision: 4350
Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c Removed: trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c Log: A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes:
- Make get_dsdt script executable.
- Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.
- Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c is correct.
- Fix broken or incorrect #include names to increase likelyhood of a successful compile.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Deleted: trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -1,237 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "northbridge/via/vx800/DrivingClkPhaseData.h" - -// DQS Driving -// Reg0xE0, 0xE1 -// According to #Bank to set DRAM DQS Driving -// #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE }; -static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE }; - -// DQ Driving -// Reg0xE2, 0xE3 -// For DDR2: According to bank to set DRAM DQ Driving -static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; -static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; - -// CS Driving -// Reg0xE4, 0xE5 -// According to #Bank to set DRAM CS Driving -// DDR1 #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; -static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44 }; -static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 }; -static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 }; - -// MAA Driving -// Reg0xE8, Reg0xE9 -static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = { - // Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 - {6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 - {18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 - {255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~ -}; - -static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = { - // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 - {6, 0x86}, // total MAB chips = 00 ~ 06 - {18, 0x86}, // total MAB chips = 06 ~ 18 - {255, 0xDB}, // total MAB chips = 18 ~ -}; - -// DCLK Driving -// Reg0xE6, 0xE7 -// For DDR2: According to #Freq to set DRAM DCLK Driving -// freq 400M, 533M, 667M, 800M -static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; -static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; - -/* - * Duty cycle - * Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB - * D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF - * According to DRAM frequency to control Duty Cycle - */ -static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30}, // 1Rank - {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00}, - {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}, -}; - -static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xED, 0x00, 0x88, 0x88, 0x84, 0x88}, // 1Rank - {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00}, - {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00}, -}; - -/* - * DRAM Clock Phase Control for FeedBack Mode - * Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 - * Processing: - * 1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode. - * 2. Program clock phase value with ChA/B DCLK enable, - * VIA_NB3DRAM_REG91[7:3]=00b - * 3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO - * ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b. - */ -static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, -}; - -static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70}, // 1Rank - {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20}, - {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30}, -}; - -/* vt6413c */ -#if 0 -static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank - {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, - {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 }, -}; -#endif - -/* vt6413d */ -static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, -}; - -/* - * DRAM Write Data phase control - * Modify NB Reg: Rx74/Rx75/Rx76 - */ -/* vt6413c */ -#if 0 -static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank - {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, - {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 }, -}; -#endif - -/* vt6413D */ -static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07}, // 1Rank - {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07}, - {0x76, 0x10, 0x80, 0x87, 0x07, 0x06}, - {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03}, -}; - -#if 0 -static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank - {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, - {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }, -}; -#endif - -/* - * DQ/DQS Output Delay Control - * Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 - */ -static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { - //RxF0 RxF1 RxF2 RxF3 - {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ -}; - -static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { - //RxF4 RxF5 RxF6 RxF7 - {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ -}; - -/* - * DQ/DQS input Capture Control - * modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B - */ -/* vt6413C */ -#if 0 -static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } -}; -#endif - -/* vt6413D */ -static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01}, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00}, - {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10} -}; - -static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x79, 0x00, 0x89, 0x89, 0x87, 0x83}, // 1Rank - {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00}, - {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10} -}; - -static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = { - //Rx70 Rx71 - {0x00, 0x05}, /* DDR800 */ - {0x00, 0x06}, /* DDR667 */ - {0x00, 0x04}, /* DDR533 */ - {0x00, 0x05}, /* DDR400 */ -}; - -static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = { - //Rx70 Rx71 - {0x00, 0x04}, /* DDR800 */ - {0x00, 0x04}, /* DDR667 */ - {0x00, 0x03}, /* DDR533 */ - {0x00, 0x04}, /* DDR400 */ -};
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-06-07 14:38:32 UTC (rev 4350) @@ -120,7 +120,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default HAVE_HARD_RESET = 0 default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 10 # FIXME. irq_table.c says 14. +default IRQ_SLOT_COUNT = 14 default HAVE_ACPI_TABLES = 1 default HAVE_OPTION_TABLE = 1 default ROM_IMAGE_SIZE = 128 * 1024
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -48,12 +48,12 @@ #include "cpu/x86/lapic/boot_cpu.c"
/* This file contains the board-special SI value for raminit.c. */ -#include "mainboard/via/6413e/DrivingClkPhaseData.c" +#include "driving_clk_phase_data.c"
#include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" #include "cpu/x86/car/copy_and_run.c" -#include "mainboard/via/6413e/wakeup.h" +#include "wakeup.h"
/* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: @@ -217,7 +217,7 @@ /* VT3409 no PCI-E */ 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie - //0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control + // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control // Set ROMSIP value by software
/* @@ -248,26 +248,27 @@ 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) - 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */ + 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) + */
// CPU Host Bus Control 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - //0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance - //0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK + // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access - //0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 + // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 - //0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL - //0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 + // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL + // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl - // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 - //0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 + // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 + // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 @@ -285,7 +286,7 @@ #define gCom1Base 0x3f8 #define gCom2Base 0x2f8
-void EmbedComInit() +void EmbedComInit(void) { u8 ByteVal; u16 ComBase; @@ -351,9 +352,7 @@
//noharddrive
- /* Set embedded COM1 I/O base = 0x3E8 */ - //D17F0RB4 - //ByteVal = 0xFD; + /* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */ if (USE_COM1 == 1) { ByteVal = (u8) ((gCom1Base >> 3) | 0x80); pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); @@ -362,9 +361,7 @@ pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); }
- /* Set embedded COM2 I/O base = 0x2E8. */ - //D17F0RB5 - //ByteVal = 0xDD; + /* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */ if (USE_COM2 == 1) { ByteVal = (u8) ((gCom2Base >> 3) | 0x80); pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal);
Copied: trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c (from rev 4349, trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "northbridge/via/vx800/driving_clk_phase_data.h" + +// DQS Driving +// Reg0xE0, 0xE1 +// According to #Bank to set DRAM DQS Driving +// #Bank 1 2 3 4 5 6 7 8 +static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE }; +static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE }; + +// DQ Driving +// Reg0xE2, 0xE3 +// For DDR2: According to bank to set DRAM DQ Driving +static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; +static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; + +// CS Driving +// Reg0xE4, 0xE5 +// According to #Bank to set DRAM CS Driving +// DDR1 #Bank 1 2 3 4 5 6 7 8 +static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; +static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44 }; +static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 }; +static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 }; + +// MAA Driving +// Reg0xE8, Reg0xE9 +static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = { + // Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 + {6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 + {18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 + {255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~ +}; + +static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = { + // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 + {6, 0x86}, // total MAB chips = 00 ~ 06 + {18, 0x86}, // total MAB chips = 06 ~ 18 + {255, 0xDB}, // total MAB chips = 18 ~ +}; + +// DCLK Driving +// Reg0xE6, 0xE7 +// For DDR2: According to #Freq to set DRAM DCLK Driving +// freq 400M, 533M, 667M, 800M +static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; +static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; + +/* + * Duty cycle + * Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB + * D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF + * According to DRAM frequency to control Duty Cycle + */ +static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30}, // 1Rank + {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00}, + {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}, +}; + +static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xED, 0x00, 0x88, 0x88, 0x84, 0x88}, // 1Rank + {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00}, + {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00}, +}; + +/* + * DRAM Clock Phase Control for FeedBack Mode + * Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 + * Processing: + * 1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode. + * 2. Program clock phase value with ChA/B DCLK enable, + * VIA_NB3DRAM_REG91[7:3]=00b + * 3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO + * ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b. + */ +static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, +}; + +static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70}, // 1Rank + {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20}, + {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30}, +}; + +/* vt6413c */ +#if 0 +static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank + {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, + {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 }, +}; +#endif + +/* vt6413d */ +static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, +}; + +/* + * DRAM Write Data phase control + * Modify NB Reg: Rx74/Rx75/Rx76 + */ +/* vt6413c */ +#if 0 +static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank + {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, + {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 }, +}; +#endif + +/* vt6413D */ +static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM][WrtData_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07}, // 1Rank + {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07}, + {0x76, 0x10, 0x80, 0x87, 0x07, 0x06}, + {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03}, +}; + +#if 0 +static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank + {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, + {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }, +}; +#endif + +/* + * DQ/DQS Output Delay Control + * Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 + */ +static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { + //RxF0 RxF1 RxF2 RxF3 + {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ +}; + +static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { + //RxF4 RxF5 RxF6 RxF7 + {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ +}; + +/* + * DQ/DQS input Capture Control + * modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B + */ +/* vt6413C */ +#if 0 +static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } +}; +#endif + +/* vt6413D */ +static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01}, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00}, + {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10} +}; + +static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x79, 0x00, 0x89, 0x89, 0x87, 0x83}, // 1Rank + {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00}, + {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10} +}; + +static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = { + //Rx70 Rx71 + {0x00, 0x05}, /* DDR800 */ + {0x00, 0x06}, /* DDR667 */ + {0x00, 0x04}, /* DDR533 */ + {0x00, 0x05}, /* DDR400 */ +}; + +static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = { + //Rx70 Rx71 + {0x00, 0x04}, /* DDR800 */ + {0x00, 0x04}, /* DDR667 */ + {0x00, 0x03}, /* DDR533 */ + {0x00, 0x04}, /* DDR400 */ +};
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -23,7 +23,7 @@ #include <arch/acpi.h> #include <../../../northbridge/via/vx800/vx800.h>
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header);
Property changes on: trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt ___________________________________________________________________ Added: svn:executable + *
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * 14, /* There can be total 14 devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-/* reboot.c from Linux. */ +/* Parts of this code is taken from reboot.c from Linux. */
/* * This file mostly copied from Rudolf's S3 patch, some changes in @@ -57,12 +57,12 @@ unsigned short pad; } __attribute__ ((packed));
-static struct Xgt_desc_struct - real_mode_gdt = - { sizeof(real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries }, - real_mode_idt = { -0x3ff, 0}, no_idt = { -0, 0}; +static struct Xgt_desc_struct real_mode_gdt = { + sizeof(real_mode_gdt_entries) - 1, + (long)real_mode_gdt_entries +}, +real_mode_idt = {0x3ff, 0}, +no_idt = { 0, 0 };
/* * This is 16-bit protected mode code to disable paging and the cache, @@ -85,16 +85,16 @@ * occurred; hopefully real BIOSs don't assume much. */
-// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */ +// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000, %eax */
static unsigned char real_mode_switch[] = { - 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ - 0x24, 0xfe, /* andb $0xfe,al */ - 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ + 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ + 0x24, 0xfe, /* andb $0xfe,al */ + 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ };
static unsigned char jump_to_wakeup[] = { - 0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */ + 0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */ };
/* @@ -103,18 +103,17 @@ * We assume that length will aways be less that 100! */ static unsigned char show31[6] = { - 0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */ + 0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */ };
static unsigned char show32[6] = { - 0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */ + 0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */ };
void acpi_jump_wake(u32 vector) { - u32 tmp; + u32 tmp, dwEip; u16 tmpvector; - u32 dwEip; u8 Data; struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
@@ -137,7 +136,7 @@ jason_tsc_count_end();
unsigned long long *real_mode_gdt_entries_at_eseg; - real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; //copy from real_mode_gdt_entries and change limition to 1M and data base to 0; + real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; /* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */ real_mode_gdt_entries_at_eseg[0] = 0x0000000000000000ULL; /* Null descriptor */ real_mode_gdt_entries_at_eseg[1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */ real_mode_gdt_entries_at_eseg[2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */ @@ -150,24 +149,25 @@ wake_thunk16_Xgt_desc[2].size = 0; wake_thunk16_Xgt_desc[2].address = 0;
- /*added this code to get current value of EIP - */ - __asm__ volatile ("calll geip\n\t" - "geip: \n\t" "popl %0\n\t":"=a" (dwEip) - ); + /* Added this code to get current value of EIP. */ + __asm__ volatile ( + "calll geip\n\t" + "geip: \n\t" + "popl %0\n\t" + : "=a" (dwEip) + );
- unsigned char *dest; - unsigned char *src; + unsigned char *dest, *src; src = (unsigned char *)dwEip; dest = WAKE_RECOVER1M_CODE; u32 i; for (i = 0; i < 0x200; i++) dest[i] = src[i];
- __asm__ __volatile__("ljmp $0x0010,%0" //08 error + __asm__ __volatile__("ljmp $0x0010,%0" /* 08 error */ ::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20)));
- /*added 0x20 "nop" to make sure the ljmp will not jump then halt */ + /* Added 0x20 "nop" to make sure the ljmp will not jump then halt. */ asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); @@ -202,104 +202,126 @@ asm volatile ("nop");
__asm__ volatile ( - /* set new esp, maybe ebp should not equal to esp?, - due to the variable in acpi_jump_wake?, anyway, this may be not a big problem. - and I didnt clear the area (ef000+-0x200) to zero. - */ - "movl %0, %%ebp\n\t" - "movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK) - ); + /* + * Set new esp, maybe ebp should not equal to esp?, due to the + * variable in acpi_jump_wake?, anyway, this may be not a big + * problem. and I didn't clear the area (ef000+-0x200) to zero. + */ + "movl %0, %%ebp\n\t" + "movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK) + );
- /* added this - only "src" and "dest" use the new stack, and the esp maybe also used in resumevector + /* + * Only "src" and "dest" use the new stack, and the esp maybe also + * used in resumevector. */ -#if PAYLOAD_IS_SEABIOS==1 - // WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c +#if PAYLOAD_IS_SEABIOS == 1 + /* WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c. */ src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000); dest = 0; - for (i = 0; i < 0xa0000; i++) //if recovered 0-e0000, then when resume, before winxp turn on the desktop screen ,there is gray background which last 1sec. + + /* + * If recovered 0-e0000, then when resume, before WinXP turn on the + * desktop screen, there is gray background which last 1sec. + */ + for (i = 0; i < 0xa0000; i++) dest[i] = src[i]; - /*__asm__ volatile ( - "movl %0, %%esi\n\t" - "movl $0, %%edi\n\t" - "movl $0xa0000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"a"(src) - );*/ - src = - (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + - 0xc0000); - //dest = 0xc0000; - //for (i = 0; i < 0x20000; i++) - // dest[i] = src[i]; - /* __asm__ volatile ( - "movl %0, %%esi\n\t" - "movl $0xc0000, %%edi\n\t" - "movl $0x20000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"a"(src) - ); */
- src = - (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + - 0xe0000 + WAKE_SPECIAL_SIZE); - //dest = 0xf0000; - //for (i = 0; i < 0x10000; i++) - // dest[i] = src[i]; - __asm__ volatile ("movl %0, %%esi\n\t" - "movl %1, %%edi\n\t" - "movl %2, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t"::"r" (src), - "r"(0xe0000 + WAKE_SPECIAL_SIZE), - "r"(0x10000 - WAKE_SPECIAL_SIZE) - ); +#if 0 + __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl $0, %%edi\n\t" + "movl $0xa0000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"a"(src) + ); +#endif + src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 + - 0x100000 + 0xc0000);
- src = - (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + - 0xf0000); - //dest = 0xf0000; - //for (i = 0; i < 0x10000; i++) - // dest[i] = src[i]; - __asm__ volatile ("movl %0, %%esi\n\t" - "movl $0xf0000, %%edi\n\t" - "movl $0x10000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src) - ); +#if 0 + dest = 0xc0000; + for (i = 0; i < 0x20000; i++) + dest[i] = src[i];
+ __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl $0xc0000, %%edi\n\t" + "movl $0x20000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"a"(src) + ); +#endif + + src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 + - 0x100000 + 0xe0000 + WAKE_SPECIAL_SIZE); + + /* dest = 0xf0000; */ + /* for (i = 0; i < 0x10000; i++) */ + /* dest[i] = src[i]; */ + __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl %1, %%edi\n\t" + "movl %2, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t"::"r" (src), + "r"(0xe0000 + WAKE_SPECIAL_SIZE), + "r"(0x10000 - WAKE_SPECIAL_SIZE) + ); + + src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 + - 0x100000 + 0xf0000); + /* dest = 0xf0000; */ + /* for (i = 0; i < 0x10000; i++) */ + /* dest[i] = src[i]; */ + __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl $0xf0000, %%edi\n\t" + "movl $0x10000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src) + ); + asm volatile ("wbinvd"); #endif /* Set up the IDT for real mode. */ asm volatile ("lidt %0"::"m" (wake_thunk16_Xgt_desc[1]));
- /* Set up a GDT from which we can load segment descriptors for real - mode. The GDT is not used in real mode; it is just needed here to - prepare the descriptors. */ + /* + * Set up a GDT from which we can load segment descriptors for real + * mode. The GDT is not used in real mode; it is just needed here to + * prepare the descriptors. + */ asm volatile ("lgdt %0"::"m" (wake_thunk16_Xgt_desc[0]));
- /* Load the data segment registers, and thus the descriptors ready for - real mode. The base address of each segment is 0x100, 16 times the - selector value being loaded here. This is so that the segment - registers don't have to be reloaded after switching to real mode: - the values are consistent for real mode operation already. */ + /* + * Load the data segment registers, and thus the descriptors ready for + * real mode. The base address of each segment is 0x100, 16 times the + * selector value being loaded here. This is so that the segment + * registers don't have to be reloaded after switching to real mode: + * the values are consistent for real mode operation already. + */ + __asm__ __volatile__( + "movl $0x0010,%%eax\n" + "\tmovl %%eax,%%ds\n" + "\tmovl %%eax,%%es\n" + "\tmovl %%eax,%%fs\n" + "\tmovl %%eax,%%gs\n" + "\tmovl %%eax,%%ss":::"eax" + );
- __asm__ __volatile__("movl $0x0010,%%eax\n" - "\tmovl %%eax,%%ds\n" - "\tmovl %%eax,%%es\n" - "\tmovl %%eax,%%fs\n" - "\tmovl %%eax,%%gs\n" "\tmovl %%eax,%%ss":::"eax"); + /* + * Jump to the 16-bit code that we copied earlier. It disables paging + * and the cache, switches to real mode, and jumps to the BIOS reset + * entry point. + */
- /* Jump to the 16-bit code that we copied earlier. It disables paging - and the cache, switches to real mode, and jumps to the BIOS reset - entry point. */ - - __asm__ - __volatile__("ljmp $0x0008,%0"::"i" - ((void *)(WAKE_THUNK16_ADDR - - sizeof(real_mode_switch) - 100))); + __asm__ __volatile__( + "ljmp $0x0008,%0"::"i" + ((void *)(WAKE_THUNK16_ADDR - sizeof(real_mode_switch) - 100)) + ); }
/* -*- linux-c -*- ------------------------------------------------------- * @@ -318,7 +340,7 @@ * Enable A20 gate (return -1 on failure) */
-//#include "boot.h" +// #include "boot.h"
#define MAX_8042_LOOPS 100000
@@ -429,9 +451,10 @@
/* Try enabling A20 through the keyboard controller */ empty_8042(); -//if (a20_test_short()) -// return 0; /* BIOS worked, but with delayed reaction */
+ // if (a20_test_short()) + // return 0; /* BIOS worked, but with delayed reaction */ + enable_a20_kbc(); if (a20_test_long()) return 0;
-
svn＠coreboot.org