Hi,
I read through the AMD 690/SB600 ACPI code and saw that src/mainboard/amd/pistachio/acpi/dsdt.asl src/mainboard/amd/dbm690t/acpi/dsdt.asl src/mainboard/technexion/tim8690/acpi/dsdt.asl all read STB5 from PCIe config space and then use the result as address of the SATA BAR5 without any proper bitmasking. For non-prefetchable 32-bit memory BARs this is OK, but if the BAR is either 64-bit or prefetchable or not memory, accesses to BAR5 will be screwed up.
Comments are appreciated. I think that SATA BAR5 is 32-bit no-prefetch memory, but since SATA does not work if I boot with 4 GB RAM, I'm pretty paranoid about everything related to 32/64 bit issues.
Regards, Carl-Daniel
Carl-Daniel Hailfinger wrote:
Hi,
I read through the AMD 690/SB600 ACPI code and saw that src/mainboard/amd/pistachio/acpi/dsdt.asl src/mainboard/amd/dbm690t/acpi/dsdt.asl src/mainboard/technexion/tim8690/acpi/dsdt.asl all read STB5 from PCIe config space and then use the result as address of the SATA BAR5 without any proper bitmasking. For non-prefetchable 32-bit memory BARs this is OK, but if the BAR is either 64-bit or prefetchable or not memory, accesses to BAR5 will be screwed up.
Isn't the BAR always memory for the SB600 SATA device?
Comments are appreciated. I think that SATA BAR5 is 32-bit no-prefetch memory, but since SATA does not work if I boot with 4 GB RAM, I'm pretty paranoid about everything related to 32/64 bit issues.
Regards, Carl-Daniel
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Carl-Daniel Hailfinger -
Stefan Reinauer