route_irq15.diff (changes pirq_routing.c): Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not getting assigned.
autoboot_delay.diff (changes filo.c): Fixes compile error when AUTOBOOT_DELAY=0.
dword_copy.diff (changes crt0.S.lb, cache_as_ram.inc (Geode LX)): Speed up copying coreboot to ram by using "movsl" instead of "movsb". Also use different console messages for copying and uncompressing, like it's already done in similar code in other places.
speed_calc.diff (changes raminit.c (Geode LX)): Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine.
await_ide.diff (changes ide.c): Made await_ide(), which polls for an ide status change, check the status reg much more often. In my case this reduced the time spent in coreboot by 1.5 sec! The timeout values of course aren't changed, only the granularity. Also, I didn't see any udelay() implementation that looked like it couldn't cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.)
fs_arch.diff (changes ext2fs.c, fat.c): #if ARCH == 'i386' results in a compile error: character constant too long (or something alike). Changed it to #ifdef __i386 I'm unsure if this is correct, though! Why didn't anyone hit this problem before? Is this some ROMCC-special?
it8712_gpio.diff (changes superio.c (IT8712F)): Added the missing I/O resources for IT8712F GPIOs. Our boards need these e.g. to switch the com ports between RS232 and RS485.
Signed-off-by: Jens Rottmann JRottmann@LiPPERTEmbedded.de ---
Above are fixes for some issues I tripped over while working on coreboot support for some of our boards. The patches can be applied in any order. (Should I have sent 7 seperate mails? I deemed it easier this way ...) I'll contribute the actual mainboard files as soon as I'm done.
Regards, Jens Rottmann
Index: src/stream/fs/ext2fs.c =================================================================== --- src/stream/fs/ext2fs.c (revision 3677) +++ src/stream/fs/ext2fs.c (working copy) @@ -239,7 +239,7 @@ * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. */ -#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long ffz (unsigned long word) { Index: src/stream/fs/fat.c =================================================================== --- src/stream/fs/fat.c (revision 3677) +++ src/stream/fs/fat.c (working copy) @@ -54,7 +54,7 @@
#define FAT_CACHE_SIZE 2048
-#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long log2 (unsigned long word) {
Index: src/superio/ite/it8712f/superio.c =================================================================== --- src/superio/ite/it8712f/superio.c (revision 3677) +++ src/superio/ite/it8712f/superio.c (working copy) @@ -129,7 +129,7 @@ {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, {&ops, IT8712F_KBCM, PNP_IRQ0,}, - {&ops, IT8712F_GPIO,}, + {&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},}, {&ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, {&ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},}, {&ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
Index: src/arch/i386/boot/pirq_routing.c =================================================================== --- src/arch/i386/boot/pirq_routing.c (revision 3677) +++ src/arch/i386/boot/pirq_routing.c (working copy) @@ -137,7 +137,7 @@ /* yet not routed */ if (!pirq[link - 1]) {
- for (k = 2; k < 15; k++) { + for (k = 2; k <= 15; k++) {
if (!((bitmap >> k) & 1)) continue;
Index: src/northbridge/amd/lx/raminit.c =================================================================== --- src/northbridge/amd/lx/raminit.c (revision 3677) +++ src/northbridge/amd/lx/raminit.c (working copy) @@ -194,7 +194,7 @@ }
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); + speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
/* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { @@ -274,15 +274,14 @@ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + - (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 2; /* -1 is a shift of 2 */ } @@ -306,14 +305,14 @@ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 2; /* -1 is a shift of 2 */ }
Index: src/boot/filo.c =================================================================== --- src/boot/filo.c (revision 3677) +++ src/boot/filo.c (working copy) @@ -18,7 +18,7 @@ #define autoboot(mem) #endif
-#ifndef AUTOBOOT_DELAY +#if !AUTOBOOT_DELAY #define autoboot_delay() 0 /* success */ #endif
Index: src/pc80/ide/ide.c =================================================================== --- src/pc80/ide/ide.c (revision 3677) +++ src/pc80/ide/ide.c (working copy) @@ -29,6 +29,7 @@ struct controller *ctrl, unsigned long timeout) { int result; + timeout *= 100; /* timeout was ms; finer granularity => reacts faster */ for(;;) { result = done(ctrl); if (result) { @@ -38,7 +39,7 @@ if (timeout-- <= 0) { break; } - udelay(1000); /* Added to avoid spinning GRW */ + udelay(10); /* Added to avoid spinning GRW */ } printk_info("IDE time out\n"); return -1;
Index: src/arch/i386/init/crt0.S.lb =================================================================== --- src/arch/i386/init/crt0.S.lb (revision 3677) +++ src/arch/i386/init/crt0.S.lb (working copy) @@ -74,6 +74,11 @@ movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx + movb %cl, %al + shrl $2, %ecx + andb $3, %al + rep movsl + movb %al, %cl rep movsb #else leal 4+_liseg, %esi @@ -215,7 +220,11 @@
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" +#if CONFIG_COMPRESS +str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n" +#else str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" +#endif str_pre_main: .string "Jumping to coreboot.\r\n" .previous
Index: src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- src/cpu/amd/model_lx/cache_as_ram.inc (revision 3677) +++ src/cpu/amd/model_lx/cache_as_ram.inc (working copy) @@ -222,6 +222,11 @@ movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx + movb %cl, %al + shrl $2, %ecx + andb $3, %al + rep movsl + movb %al, %cl rep movsb #else leal 4+_liseg, %esi @@ -363,7 +368,11 @@
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" +#if CONFIG_COMPRESS +str_copying_to_ram: .string "Uncompressing coreboot to ram.\r\n" +#else str_copying_to_ram: .string "Copying coreboot to ram.\r\n" +#endif str_pre_main: .string "Jumping to coreboot.\r\n" .previous
Jens, Thanks for the patches. I have acked and committed some of these. Please see my comments.
Jens Rottmann wrote:
route_irq15.diff (changes pirq_routing.c): Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not getting assigned.
Acked-by: Marc Jones marc.jones@amd.com r3687
autoboot_delay.diff (changes filo.c): Fixes compile error when AUTOBOOT_DELAY=0.
But this would break if AUTOBOOT_DELAY wasn't defined. Don't set AUTOBOOT_DELAY to 0 or do a more complete fix. #if AUTOBOOT_DELAY = 0 #undef AUTOBOOT_DELAY
dword_copy.diff (changes crt0.S.lb, cache_as_ram.inc (Geode LX)): Speed up copying coreboot to ram by using "movsl" instead of "movsb". Also use different console messages for copying and uncompressing, like it's already done in similar code in other places.
Acked-by: Marc Jones marc.jones@amd.com r3688
speed_calc.diff (changes raminit.c (Geode LX)): Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine.
Acked-by: Marc Jones marc.jones@amd.com r3689
await_ide.diff (changes ide.c): Made await_ide(), which polls for an ide status change, check the status reg much more often. In my case this reduced the time spent in coreboot by 1.5 sec! The timeout values of course aren't changed, only the granularity. Also, I didn't see any udelay() implementation that looked like it couldn't cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.)
Acked-by: Marc Jones marc.jones@amd.com r3690
fs_arch.diff (changes ext2fs.c, fat.c): #if ARCH == 'i386' results in a compile error: character constant too long (or something alike). Changed it to #ifdef __i386 I'm unsure if this is correct, though! Why didn't anyone hit this problem before? Is this some ROMCC-special?
I don't think anyone builds this so we wouldn't see it. We just use filo. Can you send the build output?
it8712_gpio.diff (changes superio.c (IT8712F)): Added the missing I/O resources for IT8712F GPIOs. Our boards need these e.g. to switch the com ports between RS232 and RS485.
{&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},},
I think that PNP_IO1 should be 0xfff
{&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xfff, 0}, {0xff8, 0},},
Please send new patches for the ones that need it.
Thanks, Marc
Marc,
Thanks for your help.
autoboot_delay.diff (changes filo.c): Fixes compile error when AUTOBOOT_DELAY=0.
But this would break if AUTOBOOT_DELAY wasn't defined. ...
I'm glad this patch didn't make it, because I think my English needs some fixing:
autoboot_delay.diff (changes filo.c): Fixes compile error if AUTOBOOT_DELAY=0.
Apart from that, let's make CPP speak for itself: ;-)
#include <stdio.h> #undef AUTOBOOT_DELAY
int main() { #if !AUTOBOOT_DELAY printf("Jens' patch is ok. :-)\n"); #endif return 0; }
fs_arch.diff (changes ext2fs.c, fat.c): #if ARCH == 'i386' results in a compile error: character constant too long (or something alike). Changed it to #ifdef __i386
Can you send the build output?
Sure. (Remarkable, what bzip2 compresses 600 KB text into.) As you can see, ARCH == 'i386' is mis-evaluated as FALSE, eventually choking the assembler on a PPC instruction.
I don't think anyone builds this so we wouldn't see it. We just use filo.
Funny, I thought, I was using filo, too. :-) I somehow imagined filo was, what this part of coreboot was called like ... after all, there is a file src/boot/filo.c, and unless I set AUTOBOOT_DELAY=0, I get a command line on COM1 and can load Linux kernels from any ext2 partition I like and add kernel parameters.
First I tried embedding the Linux kernel as payload in the rom, but space was really tight. With src/stream/fs_stream.c I can load the payload (= my kernel) from my ext2 root fs. This boots even faster than copying it out of the LPC rom. I think this piece of code is _really_ handy, shame if no one's using it ...
it8712_gpio.diff (changes superio.c (IT8712F)): Added the missing I/O resources for IT8712F GPIOs.
{&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},},
I think that PNP_IO1 should be 0xfff
Simple-I/O provides 1 register for each GPIO pin set 1, 2, 3, 4, 5. It occupies 5 consecutive I/O bytes with a granularity of 8. I see ITE's manual says differently, but that must be wrong, I tried it out.
Thanks again. Best regards, Jens
Jens, I am very happy to see these contributions from Lippert. I hope you or someone from this list can look at bringing them forward to v3 as well. I have used Lippert products in the past and really like them.
I look forward to seeing the board support!
thanks
ron
On 23.10.2008 01:38, ron minnich wrote:
Jens, I am very happy to see these contributions from Lippert. I hope you or someone from this list can look at bringing them forward to v3 as well.
This is the GeodeLX RAM speed calculation patch for v3.
Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine.
Signed-off-by: Jens Rottmann JRottmann@LiPPERTEmbedded.de Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: corebootv3-geodelx_speedcalc/northbridge/amd/geodelx/raminit.c =================================================================== --- corebootv3-geodelx_speedcalc/northbridge/amd/geodelx/raminit.c (Revision 946) +++ corebootv3-geodelx_speedcalc/northbridge/amd/geodelx/raminit.c (Arbeitskopie) @@ -261,7 +261,7 @@ spd_byte0 = spd_byte1;
/* Turn SPD ns time into MHz. Check what the asm does to this math. */ - speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); + speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
printk(BIOS_DEBUG, "ddr max speed is %d\n", speed); /* Current speed > max speed? */ @@ -353,15 +353,14 @@ /* Turn SPD ns time into MHz. Check what the asm does * to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + - (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { /* If -1 timing is supported, check -1 timing > GeodeLink. */ /* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */ spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHz. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed <= glspeed) { /* Set we can use -.5 timing but not -1. */ spd_byte = 31 - __builtin_clz((u32) casmap0); @@ -388,14 +387,14 @@ spd_byte = spd_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHz. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { /* If -1 timing is supported, check -1 timing > GeodeLink. */ /* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */ spd_byte = spd_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHz. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed <= glspeed) { /* Set we can use -.5 timing but not -1. */ spd_byte = 31 - __builtin_clz((u32) casmap1);
let's get someone to test this, I will have to do it next week if nobody does it before then.
ron
On 23.10.2008 04:43, ron minnich wrote:
let's get someone to test this, I will have to do it next week if nobody does it before then.
Ping?
Regards, Carl-Daniel
On Fri, Nov 7, 2008 at 6:04 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 23.10.2008 04:43, ron minnich wrote:
let's get someone to test this, I will have to do it next week if nobody does it before then.
Ping?
It will have to get done this weekend, it's been a very long week.
ron
Ühel kenal päeval, N, 2008-10-23 kell 03:41, kirjutas Carl-Daniel Hailfinger:
On 23.10.2008 01:38, ron minnich wrote:
Jens, I am very happy to see these contributions from Lippert. I hope you or someone from this list can look at bringing them forward to v3 as well.
This is the GeodeLX RAM speed calculation patch for v3.
Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine.
Signed-off-by: Jens Rottmann JRottmann@LiPPERTEmbedded.de Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Tested on ThinCan DBE63 to fix the issue of 333 > 332 comparison for RAM modules I had problems with before due to bailing out in the overclocking check.
Acked-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
Index: corebootv3-geodelx_speedcalc/northbridge/amd/geodelx/raminit.c
--- corebootv3-geodelx_speedcalc/northbridge/amd/geodelx/raminit.c (Revision 946) +++ corebootv3-geodelx_speedcalc/northbridge/amd/geodelx/raminit.c (Arbeitskopie) @@ -261,7 +261,7 @@ spd_byte0 = spd_byte1;
/* Turn SPD ns time into MHz. Check what the asm does to this math. */
- speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
printk(BIOS_DEBUG, "ddr max speed is %d\n", speed); /* Current speed > max speed? */
@@ -353,15 +353,14 @@ /* Turn SPD ns time into MHz. Check what the asm does * to this math. */
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) +(spd_byte & 0x0F)));
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { /* If -1 timing is supported, check -1 timing > GeodeLink. */ /* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */ spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHz. Check what the asm does to this math. */
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed <= glspeed) { /* Set we can use -.5 timing but not -1. */ spd_byte = 31 - __builtin_clz((u32) casmap0);@@ -388,14 +387,14 @@ spd_byte = spd_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHz. Check what the asm does to this math. */
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { /* If -1 timing is supported, check -1 timing > GeodeLink. */ /* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */ spd_byte = spd_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHz. Check what the asm does to this math. */
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed <= glspeed) { /* Set we can use -.5 timing but not -1. */ spd_byte = 31 - __builtin_clz((u32) casmap1);
On 18.03.2009 18:32, Mart Raudsepp wrote:
Ühel kenal päeval, N, 2008-10-23 kell 03:41, kirjutas Carl-Daniel Hailfinger:
On 23.10.2008 01:38, ron minnich wrote:
Jens, I am very happy to see these contributions from Lippert. I hope you or someone from this list can look at bringing them forward to v3 as well.
This is the GeodeLX RAM speed calculation patch for v3.
Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine.
Signed-off-by: Jens Rottmann JRottmann@LiPPERTEmbedded.de Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Tested on ThinCan DBE63 to fix the issue of 333 > 332 comparison for RAM modules I had problems with before due to bailing out in the overclocking check.
Acked-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
Thanks, committed in r1157.
Regards, Carl-Daniel
Hi Jens,
can you please check if all of your patches have been applied? I want to make sure no patches are lost.
Thanks!
Regards, Carl-Daniel
On 21.10.2008 11:18, Jens Rottmann wrote:
route_irq15.diff (changes pirq_routing.c): Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not getting assigned.
autoboot_delay.diff (changes filo.c): Fixes compile error when AUTOBOOT_DELAY=0.
dword_copy.diff (changes crt0.S.lb, cache_as_ram.inc (Geode LX)): Speed up copying coreboot to ram by using "movsl" instead of "movsb". Also use different console messages for copying and uncompressing, like it's already done in similar code in other places.
speed_calc.diff (changes raminit.c (Geode LX)): Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine.
await_ide.diff (changes ide.c): Made await_ide(), which polls for an ide status change, check the status reg much more often. In my case this reduced the time spent in coreboot by 1.5 sec! The timeout values of course aren't changed, only the granularity. Also, I didn't see any udelay() implementation that looked like it couldn't cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.)
fs_arch.diff (changes ext2fs.c, fat.c): #if ARCH == 'i386' results in a compile error: character constant too long (or something alike). Changed it to #ifdef __i386 I'm unsure if this is correct, though! Why didn't anyone hit this problem before? Is this some ROMCC-special?
it8712_gpio.diff (changes superio.c (IT8712F)): Added the missing I/O resources for IT8712F GPIOs. Our boards need these e.g. to switch the com ports between RS232 and RS485.
Signed-off-by: Jens Rottmann JRottmann@LiPPERTEmbedded.de
Hi Carl-Daniel,
can you please check if all of your patches have been applied?
Yes, all my patches were applied to v2 about 4 months ago.
I don't know if the patches are also suitable / necessary for v3. I have never worked with v3 so far. To my knowledge, the speed calculation patch is the only one that was ported to v3, too, by Ron Minnich.
Best regards, Jens Rottmann
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Carl-Daniel Hailfinger -
Jens Rottmann -
Marc Jones -
Mart Raudsepp -
ron minnich