Re: [coreboot] Intel Leaf Hill Coreboot Trouble

[Cameron Craig]

Hi all,

I have enabled post codes and all the debug config options in coreboot that looked useful.

As Paul has already done, I have narrowed down the latest issue to the FspSiliconInit() stage (FSP-S).
The 0x93 post code is the last message I get on the serial console, and signifies that FspSiliconInit() has started but not completed.
See (https://github.com/coreboot/coreboot/blob/master/src/include/console/post_co...).

I have attached the full serial log.

I can’t see how the actual FSP blob could be at fault here.

I don’t know if this is of help, but I came across this document:
https://github.com/IntelFsp/FSP/raw/ApolloLake/ApolloLakeFspBinPkg/Docs/Apol...

Specifically section 3.5.4:
“It is expected that boot loader will program MTRRs for SBSP as needed after TempRamExit but before entering FspSiliconInit. If MTRRs are not programmed properly, the boot performance might be impacted.”

This “boot performance” may be part of the issue?

Any thoughts would be appreciated, this mailing list has been helpful so far!

Cheers,
Cameron

Cameron Craig | Graduate Software Engineer | Exterity Limited
tel: [phone] | fax:
e: [e-mail] | w: www.exterity.com

From: Cameron Craig
Sent: 02 October 2017 11:19
To: Cameron Craig; 'Paul Penz'; [e-mail]
Subject: RE: Re: [coreboot] Intel Leaf Hill Coreboot Trouble

Hi Paul,

Those changes to the IFWI blob worked great, thanks!
I have attached the serial console log. It looks like we are in similar situations now.

I got a hang of around 45s at “MRC: region file invalid in 'RW_VAR_MRC_CACHE”,
and then it hangs indefinitely at the end of the log.

I tracked the MRC cache message down to this line:
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/mrc_ca...

I’m stuck again for the moment. Thanks again Paul for getting me one step closer.

Cheers,
Cameron

From: coreboot [mailto:[e-mail]] On Behalf Of Cameron Craig
Sent: 28 September 2017 16:51
To: 'Paul Penz'; [e-mail]
Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble

Hi Paul,

Great to hear I’m not the only one in this situation ☺

I’ve just been using the IWFI file from Intel with no modifications,  so I’ll look out the FIT tool and give that a go.

Thanks,
Cameron

Cameron Craig | Graduate Software Engineer | Exterity Limited
tel: [phone] | fax:
e: [e-mail] | w: www.exterity.comhttp://www.exterity.com

From: coreboot [mailto:[e-mail]] On Behalf Of Paul Penz
Sent: 28 September 2017 15:35
To: [e-mail]
Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble

Hi Cameron,

I had the same problem.

Had you modified the intel IFWI file ?

If not, I had done this additional:

Download 522538_apl txe hf 3.0.11.1131 (th2 & rs1).zip from intel
Start fit.exe
Load the IFWI file
Change at Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00
Change at Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0
Save

Now I get output on the console and postcodes, but during FSP_M a long pause of ca. 45s exists and it hangs later during FSP_P initialization.

Good luck
Paul

Paul Penz
Dipl.-Ing. (FH)
Senior Hardware Engineer

ELTEC Elektronik AG, Mainz
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