Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init

[Zoran Stojsavljevic]

Hello Andy,

I would advise to you to try the same coreboot with DIMM or SIMM INTEL
Rangeley based CRB, and see if this does work, for some reason? Couple of
experiments more with different CRBs with different memory configurations
would not make too much headaches, don't you think?

If you do not use BCT tool, the following is true. You should use Binary
Configuration TOOL (BCT) to change some configuration parameters for
Rangeley (you should have in Rangeley FSP package also included BCT)!

*As previously discussed, even though Intel FSP is a binary file, it needs
a provision to customize its internal states and features; therefore, it
has reserved a data region inside the binary for customization. The data
area also contains a couple of platform-specific parameters that Intel FSP
would otherwise have no knowledge about, or would initialize the board with
default values. The Boot Setting File (BSF) plays an important role for
this purpose. It is basically a text file that contains firmware internal
settings associated with the board; for example, the SMBUS (System
Management Bus) address of a SPD (Serial Presence Detect) ROM on a DIMM
(Dual Inline Memory Module) is one of the data in the BSF.*

*$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_DEFAULT_ = 0xA0*
*$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_DEFAULT_ = 0xA2*

*The data in BSF is represented in a GUI-based tool, which allows
developers to visualize the meaning of each component in BSF. With the GUI
and BSF, it is collectively called a Binary Configuration Tool (BCT). There
are three versions of BCT: one runs under Windows, one runs under Linux,
and the third is a command-line option under Linux.*

Please, search for the book called:  *Embedded Firmware Solutions
[describing INTEL FSP]...*

And search for Chapter 3. There, everything is explicitly well
explained/organized.

Hope this helps,
Zoran

On Fri, Jan 20, 2017 at 1:47 PM, Andy Knowles <
[e-mail]> wrote:
> I’m trying to bring up an Intel Rangeley based prototype board using
> coreboot and Intel FSP. During FspInitEntry, FSP prints:
>
> Err[24]: GetSet Value exceeds limits
>
> to serial debug and halts. Does anyone know what this means?
>
> I’m using the Memory Down option in the FSP and filling in the
> MEM_DOWN_DIMM_CONFIG structure in mainboard/…/romstage.c
>
> I can see that the FSP is reading and validating this structure, as
> changing the ram speed has an effect on memory clock frequency, and if I
> put in invalid values the FSP will complain. I’ve tried reducing memory
> speed, disabling ECC, disabling channel 1 but I always get the same error.
>
> Does anyone else have any experience with Memory Down on Rangeley?
>
> Andy Knowles