New patch to review for coreboot: 68ae18e F15tn: Fix all warnings, enable warnings as errors
Martin Roth (martin.roth@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2171
-gerrit
commit 68ae18e5cd6a728a1d4d1b7a71a201e2caaee330 Author: Martin Roth martin.roth@se-eng.com Date: Thu Jan 17 16:28:30 2013 -0700
F15tn: Fix all warnings, enable warnings as errors
Enable 'all warnings being treated as errors' in thatcher and parmer.
Fixed the following warnings on parmer / thatcher: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c: In function 'GetPstateGatherDataAddressAtPost': src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c: In function 'MemNInitNBDataTN': src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23: warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0: src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0: warning: "LOCAL_APIC_ADDR" redefined [enabled by default] src/include/cpu/x86/lapic_def.h:9:0: note: this is the location of the previous definition
In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0, from src/mainboard/amd/parmer/mainboard.c:28: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition
Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801 Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/mainboard/amd/parmer/Kconfig | 4 - src/mainboard/amd/parmer/devicetree.cb.min | 85 +++++++++ src/mainboard/amd/parmer/devicetree.cb.orig | 199 +++++++++++++++++++++ src/mainboard/amd/parmer/devicetree_fan.cb | 133 ++++++++++++++ src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/thatcher/Kconfig | 4 - src/mainboard/amd/thatcher/mainboard.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- .../f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c | 4 +- .../amd/agesa/f15tn/Proc/CPU/cpuPostInit.c | 2 +- .../amd/agesa/f15tn/Proc/CPU/cpuRegisters.h | 4 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c | 4 +- src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h | 2 +- 15 files changed, 432 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index e3b153d..8973cb5 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -100,8 +100,4 @@ config VGA_BIOS_ID string default "1002,9900"
-config WARNINGS_ARE_ERRORS - bool - default n - endif # BOARD_AMD_PARMER diff --git a/src/mainboard/amd/parmer/devicetree.cb.min b/src/mainboard/amd/parmer/devicetree.cb.min new file mode 100644 index 0000000..32f5484 --- /dev/null +++ b/src/mainboard/amd/parmer/devicetree.cb.min @@ -0,0 +1,85 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15tn/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 on end # PCIE SLOT0 x16 + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 +# device pci 14.6 on end # Gec + device pci 14.7 on end + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #southbridge/amd/hudson + device pci 18.0 on end + #device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/parmer/devicetree.cb.orig b/src/mainboard/amd/parmer/devicetree.cb.orig new file mode 100644 index 0000000..ff2ca1a --- /dev/null +++ b/src/mainboard/amd/parmer/devicetree.cb.orig @@ -0,0 +1,199 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15tn/root_complex +<<<<<<< Updated upstream + device lapic_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 on end # PCIE SLOT0 x16 + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 +# device pci 14.6 on end # Gec + device pci 14.7 on end + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #southbridge/amd/hudson + device pci 18.0 on end + #device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #pci_domain +======= + + device lapic_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 0 on end + end + end + + device pci_domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 on end # PCIE SLOT0 x16 + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + + #set up Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x0F, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x18, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/agesa/family15tn + end #pci_domain +>>>>>>> Stashed changes +end #northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/parmer/devicetree_fan.cb b/src/mainboard/amd/parmer/devicetree_fan.cb new file mode 100644 index 0000000..0efdac0 --- /dev/null +++ b/src/mainboard/amd/parmer/devicetree_fan.cb @@ -0,0 +1,133 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15tn/root_complex + + device lapic_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device pci_domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 on end # PCIE SLOT0 x16 + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + + #set up Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x0F, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x18, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + + end #chip northbridge/amd/agesa/family15tn + end #pci_domain +end #northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index a83cd42..7c5dfc0 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -22,10 +22,10 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> +#include "BiosCallOuts.h" #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <arch/acpi.h> -#include "BiosCallOuts.h" #include <cpu/amd/agesa/s3_resume.h> #include "agesawrapper.h"
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 7700034..f529dc2 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -101,8 +101,4 @@ config VGA_BIOS_ID string default "1002,9917"
-config WARNINGS_ARE_ERRORS - bool - default n - endif # BOARD_AMD_THATCHER diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index bc1d591..d1c389c 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -22,10 +22,10 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> +#include "BiosCallOuts.h" #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <arch/acpi.h> -#include "BiosCallOuts.h" #include <cpu/amd/agesa/s3_resume.h> #include "agesawrapper.h"
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 9318164..3a29009 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -29,12 +29,12 @@ #include <lib.h> #include <cpu/cpu.h> #include <cbmem.h> +#include <AGESA.h>
#include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h>
#include <Porting.h> -#include <AGESA.h> #include <Options.h> #include <Topology.h> #include <cpu/amd/amdfam15.h> diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c index ffb33ab..4038181 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -288,5 +288,5 @@ GetGlobalCpuFeatureListAddress (
AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
- *Address = (UINT64 *)(AddressValue); + *Address = (UINT64 *)(intptr_t)(AddressValue); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c index af00f26..525bb1d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c @@ -242,7 +242,7 @@ SaveDeviceContext ( UINT64 EndAddress; VOID *OrMask;
- StartAddress = (UINT64)DeviceList; + StartAddress = (UINT64)(intptr_t)DeviceList; Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
@@ -306,7 +306,7 @@ SaveDeviceContext ( break; } } - EndAddress = (UINT64) OrMask; + EndAddress = (UINT64)(intptr_t)OrMask; *ActualBufferSize = (UINT32) (EndAddress - StartAddress); }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c index 5eda346..460955e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c @@ -232,7 +232,7 @@ GetPstateGatherDataAddressAtPost (
AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
- *Ptr = (UINT64 *)(AddressValue); + *Ptr = (UINT64 *)(intptr_t)(AddressValue);
return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h index 173044c..96e6c7f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h @@ -375,7 +375,11 @@ typedef struct { #define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull #define APIC_EXT_BRDCST_MASK 0x000E0000ul #define APIC_ENABLE_BIT 0x00000800ul + +#ifndef LOCAL_APIC_ADDR #define LOCAL_APIC_ADDR 0xFEE00000ul +#endif + #define INT_CMD_REG_LO 0x300 #define INT_CMD_REG_HI 0x310 #define REMOTE_MSG_REG 0x380 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c index 63f255b..b93f4b6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c @@ -350,7 +350,7 @@ MemNInitNBDataTN ( NBPtr->ProgramCycTimings = MemNProgramCycTimingsUnb; NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; NBPtr->HtMemMapInit = MemNHtMemMapInitTN; - NBPtr->SyncAddrMapToAllNodes = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; + NBPtr->SyncAddrMapToAllNodes = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; NBPtr->CpuMemTyping = MemNCPUMemTypingNb; NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingTN; NBPtr->AfterDqsTraining = MemNAfterDQSTrainingTN; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c index e203fd0..13900cd 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c @@ -514,13 +514,13 @@ MemNInsDlyCompareTestPatternNb ( * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK */ -BOOLEAN +VOID MemNTrainingFlowUnb ( IN OUT MEM_NB_BLOCK *NBPtr ) { memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); - return TRUE; + return; } /*---------------------------------------------------------------------------- * LOCAL FUNCTIONS diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h index 6174c98..98a78f1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h @@ -1417,7 +1417,7 @@ GetTrainDlyFromHeapNb ( IN DRBN Drbn );
-BOOLEAN +VOID MemNTrainingFlowUnb ( IN OUT MEM_NB_BLOCK *NBPtr );
-
Martin Roth