Dear Lance,
Thank you for your reply.
On Mon, Feb 25, 2019 at 4:27 AM Lance Zhao lance.zhao@gmail.com wrote:
Current coreboot should have same level of microcode compare to intel-microcode for Linux.
Indeed. I saw a commit updating Intel microcode in last December, so I am sure the microcode is not so ancient that it does not contain the fix for a known errata.
Best regards, Masanori
Hello Masanori,
sorry for the late reply, I guess I could have saved you from some confusion.
Am 26.02.19 um 05:35 schrieb Masanori Ogino:
On Mon, Feb 25, 2019 at 4:27 AM Lance Zhao lance.zhao@gmail.com wrote:
Current coreboot should have same level of microcode compare to intel-microcode for Linux.
Indeed. I saw a commit updating Intel microcode in last December, so I am sure the microcode is not so ancient that it does not contain the fix for a known errata.
Yes, coreboot's microcode should be up to date. However, in your log, it never tries to apply the update, it seems (it should tell something about the `cpu_microcode_blob.bin`). I also can't find any call in the current source that would try to update microcode, so this might be a recent regression.
If anybody wants to look into this, one clue so far: in `src/cpu/ intel/model_1067x/mp_init.c` a `.get_microcode_info` pointer seems to be missing in the `struct mp_ops`. Also, the microcode should be updated once in advance for the BSP. This could be done early in the bootblock (as it is for `cpu/intel/model_206ax/`) or later, e.g. right before running mp_init_with_smm().
Nico
Dear Nico,
Thank you for your explanation.
On Tue, Feb 26, 2019 at 10:09 PM Nico Huber nico.huber@secunet.com wrote:
Yes, coreboot's microcode should be up to date. However, in your log, it never tries to apply the update, it seems (it should tell something about the `cpu_microcode_blob.bin`). I also can't find any call in the current source that would try to update microcode, so this might be a recent regression.
Ah, yes, the regression seems to be introduced when parallel MP initialization had been enabled for Intel Core 2 family according to the commit log of related directories. I will check out and test a revision just before the change.
If anybody wants to look into this, one clue so far: in `src/cpu/ intel/model_1067x/mp_init.c` a `.get_microcode_info` pointer seems to be missing in the `struct mp_ops`. Also, the microcode should be updated once in advance for the BSP. This could be done early in the bootblock (as it is for `cpu/intel/model_206ax/`) or later, e.g. right before running mp_init_with_smm().
Best regards, Masanori
Hello,
I was recently made aware of a change in coreboot's gerrit which may address this issue: https://review.coreboot.org/c/coreboot/+/31600
Best regards,
Angel Pons Pons
Dear Angel,
On Wed, Feb 27, 2019 at 8:45 PM Angel Pons th3fanbus@gmail.com wrote:
I was recently made aware of a change in coreboot's gerrit which may address this issue: https://review.coreboot.org/c/coreboot/+/31600
Thank you for pointing this out. I will cherry-pick and test it if desired. (Should I test https://review.coreboot.org/c/coreboot/+/30775 first?)
Best regards, Masanori
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Angel Pons -
Masanori Ogino -
Nico Huber