Author: uwe Date: Thu Feb 3 00:49:41 2011 New Revision: 6327 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6327
Log: Add detection/dump support for the NSC PC87382.
It is a rather small 'Super I/O' device, containing a serial port, IR, GPIO, and a Docking LPC switch. It is used in various Thinkpads.
Add 0x164e/0x16ef to the list of probed ports for NSC chips, as Thinkpads are using this address pair.
Signed-off-by: Sven Schnelle svens@stackframe.org Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/util/superiotool/nsc.c trunk/util/superiotool/superiotool.h
Modified: trunk/util/superiotool/nsc.c ============================================================================== --- trunk/util/superiotool/nsc.c Tue Feb 1 20:19:53 2011 (r6326) +++ trunk/util/superiotool/nsc.c Thu Feb 3 00:49:41 2011 (r6327) @@ -305,7 +305,25 @@ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, {EOT}}}, - + {0xf4, "PC87382", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x26,0x27,0x29,EOT}, + {0xf4,0x11,0x63,0x00,0x00,0x00,EOT}}, + {0x02, "IR", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x03, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x07, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1, + 0xf2,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC, + 0x01,EOT}}, + {0x19, "Docking LPC switch", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,EOT}}, + {EOT}}}, /* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */ {0xea, "PC8739x", { {NOLDN, NULL,
Modified: trunk/util/superiotool/superiotool.h ============================================================================== --- trunk/util/superiotool/superiotool.h Tue Feb 1 20:19:53 2011 (r6326) +++ trunk/util/superiotool/superiotool.h Thu Feb 3 00:49:41 2011 (r6327) @@ -223,7 +223,7 @@ {probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}}, /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ {probe_idregs_ite, {0x25e, 0x2e, 0x4e, 0x370, EOT}}, - {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, + {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, 0x164e, EOT}}, /* I/O pairs on Nuvoton EC chips can be configured by firmware in * addition to the following hardware strapping options. */ {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}},