Author: stepan Date: Tue Apr 13 12:04:35 2010 New Revision: 5418 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5418
Log: use the standard udelay on sc520.
Acked-by: Stefan Reinauer stepan@coresystems.de Signed-off-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/src/cpu/amd/sc520/raminit.c trunk/src/cpu/amd/sc520/sc520.c
Modified: trunk/src/cpu/amd/sc520/raminit.c ============================================================================== --- trunk/src/cpu/amd/sc520/raminit.c Tue Apr 13 12:01:14 2010 (r5417) +++ trunk/src/cpu/amd/sc520/raminit.c Tue Apr 13 12:04:35 2010 (r5418) @@ -234,18 +234,7 @@ *ptr = 0; }
-void sc520_udelay(int microseconds) { - volatile int x; - for(x = 0; x < 1000; x++) - ; -} - -/* looks like we define this now */ -void -udelay(int microseconds) { - sc520_udelay(microseconds); -} - +#include "pc80/udelay_io.c"
static void dumpram(void){ print_err("ctl "); print_err_hex8(*drcctl); print_err("\n"); @@ -311,7 +300,7 @@ print_err("NOP\n"); /* 100? 200? */ udelay(100); - print_err("after sc520_udelay\n"); + print_err("after udelay\n");
/* issue all banks precharge */ *drcctl=0x02; @@ -385,8 +374,8 @@ dummy_write(); print_err("NOP\n"); /* 100? 200? */ - //sc520_udelay(100); - print_err("after sc520_udelay\n"); + //udelay(100); + print_err("after udelay\n");
/* issue all banks precharge */ *drcctl=0x02;
Modified: trunk/src/cpu/amd/sc520/sc520.c ============================================================================== --- trunk/src/cpu/amd/sc520/sc520.c Tue Apr 13 12:01:14 2010 (r5417) +++ trunk/src/cpu/amd/sc520/sc520.c Tue Apr 13 12:04:35 2010 (r5418) @@ -15,19 +15,6 @@ #include <delay.h> #include "chip.h"
- -/* hack for now */ -static void sc520_udelay(int microseconds) { - volatile int x; - for(x = 0; x < 1000; x++) - ; -} - -/* looks like we define this now */ -void -udelay(unsigned microseconds) { - sc520_udelay(microseconds); -} /* * set up basic things ... * PAR should NOT go here, as it might change with the mainboard.