[v2] r4186 - in trunk/coreboot-v2/src: config mainboard/arima/hdama mainboard/dell/s1850 mainboard/intel/jarrell mainboard/intel/mtarvon mainboard/intel/truxton mainboard/intel/xe7501devkit mainboard/kontron/986lcd-m mainboard/supermicro/x6dai_g mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2 mainboard/supermicro/x6dhr_ig mainboard/supermicro/x6dhr_ig2

Author: hailfinger
Date: 2009-04-23 00:08:00 +0200 (Thu, 23 Apr 2009)
New Revision: 4186

Added:
   trunk/coreboot-v2/src/config/nofailovercalculation128.lb
Modified:
   trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
   trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb
   trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb
Log:
Convert 12 more boards to use include statements in Config.lb.

Signed-off-by: Carl-Daniel Hailfinger 
Acked-by: Peter Stuge

Added: trunk/coreboot-v2/src/config/nofailovercalculation128.lb
===================================================================
--- trunk/coreboot-v2/src/config/nofailovercalculation128.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/config/nofailovercalculation128.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -0,0 +1,38 @@
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The coreboot bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreboot will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE = 128 * 1024
+default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
+
+## This is needed to work around a parser bug.
+if USE_FALLBACK_IMAGE
+end
+

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -1,38 +1,6 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -3,41 +3,9 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -3,41 +3,9 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -17,40 +17,9 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot ROM chip
-##
-if USE_FALLBACK_IMAGE
-        default ROM_SECTION_SIZE = FALLBACK_SIZE
-        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-        default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
-        default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of the coreboot bootloader
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot ROM
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -17,40 +17,9 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot ROM chip
-##
-if USE_FALLBACK_IMAGE
-        default ROM_SECTION_SIZE = FALLBACK_SIZE
-        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-        default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
-        default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of the coreboot bootloader
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot ROM
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -1,40 +1,5 @@
-##################################################################
-## BEGIN BOILERPLATE - DO NOT EDIT
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus payload) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
+include /config/nofailovercalculation128.lb

-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-
-else
-# The normal image goes at the beginning of the coreboot ROM region
-# and uses all the remaining space
-
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-default XIP_ROM_SIZE = 65536
-default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )
-
-## END BOILERPLATE
-##################################################################
-
 arch i386 end

##

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -28,41 +28,9 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-        default ROM_SECTION_SIZE   = FALLBACK_SIZE
-        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-        default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-        default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation.lb

##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=(64*1024)
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -3,41 +3,9 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can be cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -3,39 +3,8 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE	=( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can be cached to speed up coreboot.
-## execution speed.
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -3,39 +3,8 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE	=( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can be cached to speed up coreboot.
-## execution speed.
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -3,41 +3,9 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb	2009-04-22 20:41:42 UTC (rev 4185)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb	2009-04-22 22:08:00 UTC (rev 4186)
@@ -3,41 +3,9 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb

##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##