Hi all,
We're developing a new board based in the AMD Prairie Falcon and the closest coreboot is from amd/gardenia.
We're using coreboot verion 4.9.
Now we have console but we have a reset loop once the 'AmdInitPost' from src/soc/amd/common/block/pi/agesawrapper.c
is called. I've modified the smbus_spd.c to display the SPD content. This is the log we get:
coreboot-4.9-7f520c8fe6fc991df2c4e91f42843d4290744ebb Thu Jun 20 13:05:42 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x8000800 SyncFlood BIT11 CBFS @ 200 size 7ffe00 CBFS: 'Master Header Locator' located CBFS at [200:800000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 6d04
coreboot-4.9-7f520c8fe6fc991df2c4e91f42843d4290744ebb Thu Jun 20 13:05:42 UTC 2019 romstage starting... CBFS @ 200 size 7ffe00 CBFS: 'Master Header Locator' located CBFS at [200:800000) CBFS: Locating 'smu_fw' CBFS: Found @ offset bdc00 size 12262 PSP: Load blob type 19 from @ff8bde38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS @ 200 size 7ffe00 CBFS: 'Master Header Locator' located CBFS at [200:800000) CBFS: Locating 'AGESA' CBFS: Found @ offset 5ffdc0 size 662d4 agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS POST: 0x40 agesawrapper_amdinitpost() entry DRAM clear on reset: Keep WEAK: src/soc/amd/stoneyridge/BiosCallOuts.c/mainboard_read_spd called -------------READING SPD----------- iobase: 0x00000B00, SmbusSlave: 0x000000A4, count: 512 23 11 0C 02 85 21 00 08 00 60 00 03 01 03 00 00 00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A 20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36 16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 9E 78 11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53 23 11 0C 02 85 21 00 08 00 60 00 03 01 03 00 00 00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A 20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36 16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 9E 78 11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53 -------------FINISHED READING SPD-----------
And again...
We only have one dimm connected, the A4. Is defined in devicetree.cb
register "spd_addr_lookup" = " { { {0xA4, 0x00} }, // socket 0 - Channel 0, slots 0 & 1 }"
and I've modified OemCustomize.c to set
#define DIMMS_PER_CHANNEL 1
Attached is the .config I'm using...
What can I check now? Any suggestion is welcome!
-
Jorge Fernandez Monteagudo