memory speed downgrade is only need if you have 8 dimm 4g installed with 400Mhz, and it should be set to 266Mhz..... 8 dimm 2g installed with 400Mhz, and it should be set to 333Mhz.....
Do we have such MB to be supportd except 4 rank dimm?
YH
-----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Monday, May 02, 2005 7:29 AM To: Tao Liu Cc: LinuxBIOS Subject: Re: [LinuxBIOS] Opteron memclk speed/loading fix
- Tao Liu liutao1980@gmail.com [050430 11:01]:
Hello,
the following patch fixes memclk selection on different
loadings for
opteron, it is useful if you have more than 4dimms for one
opteron cpu.
Was someone able to test this on a couple of systems? Should it be commited to the repository?
Stefan
LinuxBIOS mailing list LinuxBIOS@openbios.org http://www.openbios.org/mailman/listinfo/linuxbios
Hello,
we are building an 1 cpu 8 dimm board and experienced this problem, and accroding to amd's amd64 bios developers' guide memory speed downgrade should also be applyed to the following 4dimm configurations:
(1) 4 dimm with more than 2 double-rank dimms, downgrade to 333MHz (2) more than 1 double-rank dimm for single channel, downgrade to 333MHz
Tao
On 5/3/05, YhLu YhLu@tyan.com wrote:
memory speed downgrade is only need if you have 8 dimm 4g installed with 400Mhz, and it should be set to 266Mhz..... 8 dimm 2g installed with 400Mhz, and it should be set to 333Mhz.....
Do we have such MB to be supportd except 4 rank dimm?
YH
Tao Liu liutao1980@gmail.com writes:
Hello,
we are building an 1 cpu 8 dimm board and experienced this problem, and accroding to amd's amd64 bios developers' guide memory speed downgrade should also be applyed to the following 4dimm configurations:
(1) 4 dimm with more than 2 double-rank dimms, downgrade to 333MHz (2) more than 1 double-rank dimm for single channel, downgrade to 333MHz
In principle I agree with this. However those are guidelines and it stated that the actual details may very per motherboard.
So for merging I would request we have a generic function that performs this logic, and have the generic call in raminit.c make a motherboard specific call. By default that motherboard specific call would simply call the default generic method, but a motherboard that has better memory stability could override this.
Eric
On 06 May 2005 08:55:20 -0600, Eric W. Biederman ebiederman@lnxi.com wrote:
In principle I agree with this. However those are guidelines and it stated that the actual details may very per motherboard.
So for merging I would request we have a generic function that performs this logic, and have the generic call in raminit.c make a motherboard specific call. By default that motherboard specific call would simply call the default generic method, but a motherboard that has better memory stability could override this.
Eric
I think we can create a mem speed table for each mem controller, the table has 5 columns: dimms, how many dimms max for this configuration 1rank, how many 1rank dimms max for this configuration 2rank, .... 4rank, .... speed, the max speed for this configuration
so for a normal mainboard the table should be: dimms, 1rank, 2rank, 4rank, speed 8, 8, 8, 8, 333 4, 4, 4, 4, 333 4, 4, 2, 0, 400 4, 4, 0, 2, 400 0, 0, 0, 0, 0 (the end)
and for a mainboard can work with 4 4rank dimms the table maybe: dimms, 1rank, 2rank, 4rank, speed 8, 8, 8, 8, 333 4, 4, 4, 4, 400 0, 0, 0, 0, 0 (the end)
in raminit.c we analyse this table and get the max speed for each mem controller of this mainboard. for single channel case we divide the first four column values by 2 and get the correct configuration. I don't know whether there are 3rank dimms, if yes maybe we should have the 3rank column.
Tao
Hello,
attached is the patch which implements the mem speed table, mainboards describe it's mem speed ability in mem_controller structure as the following example:
static const struct mem_controller cpu[] = { { .node_id = 0, .f0 = PCI_DEV(0, 0x18, 0), .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), .channel0 = { (0xa<<3)|0, (0xa<<3)|2, (0xa<<3)|4, (0xa<<3)|6 }, .channel1 = { (0xa<<3)|1, (0xa<<3)|3, (0xa<<3)|5, (0xa<<3)|7 }, .memclk_conf = { {4, 4, 2, 0, 0, 200}, /* 200M for: 4x1rank, 2x1rank + 2x2rank, etc */ {4, 4, 0, 2, 0, 200}, {4, 4, 0, 0, 2, 200}, {8, 8, 8, 8, 8, 166}, /* 166M for other case */ {0, 0, 0, 0, 0, 0}, /* the end */ } }, };
Tao
-
ebiederman＠lnxi.com -
Tao Liu -
YhLu