Re: [coreboot] GSoC project ideas

[Oliver Schinagl]

On 03/12/12 19:07, Svetoslav Trochev wrote:
> Hi Carl-Daniel,
>
> I don't qualify as GSoC student (too old ;) ). For sure I can't be

I don't think age matters, as long as you are an student at a recognized 
school, google approves.
> mentor because I am absolute newbie here, but I am interested to find
> out If I can help with one of those projects. I know the theory how
> those things are working, but I have zero experience. Do you think I
> can be useful even if it is outside the GSoC program?
>
> Thanks,
> Svetoslav Trochev
>
> On Sat, Mar 10, 2012 at 12:27 PM, Carl-Daniel Hailfinger
>   wrote:
> > Hi,
> >
> > given the lack of affordable and available hardware tools for coreboot
> > development, I propose to look for a different set of projects this
> > year: Tools which would help developers, and which are usable especially
> > with current hardware. A list of ideas follows.
> > Flash ICE device with SPI support.
> > Flash ICE device with LPC/FWH support.
> > Serial emulation for LPC buses on a configurable I/O port with USB
> >
> > output on the other side.
> > Dual serial emulation for two LPC buses either on the same device or
> >
> > with two identical devices and a fast bus in between.
> > Serial emulation for PCI buses (i.e. PCI/serial card).
> >
> > The reason for the flash ICE devices is obvious: Avoid external
> > reflashing while you're developing.
> >
> > The serial emulation or similar POST code port emulation is meant to
> > provide a serial console, a SerialICE connection and/or some POST code
> > output channel. This is especially important for laptops where debugging
> > can be a pain and where you usually have a LPC bus available in the
> > MiniPCIe slot.
> >
> > The dual serial emulation for two LPC buses would work as a fast
> > PC-to-PC connection for SerialICE and other purposes where you need low
> > latency, not necessarily high throughput.
> >
> > The serial emulation for PCI buses would complement the serial emulation
> > for LPC to provide an easy way to connect to a SerialICE instance on the
> > other side.
> >
> > As a basis for all those ideas I'd propose the Openbench logic sniffer.
> > It has a fast FPGA, enough gates and roughly 32 kByte RAM. The FPGA is
> > fast enough and big enough to accommodate the necessary logic, and we
> > could easily attach a fast (66+ MHz) SPI flash chip to it. And with $50
> > incl. shipping the OLS is not extremely cheap, but worth its price and
> > easily available. Fast flash chips are also available for reasonable prices.
> >
> > All of those projects would not result in any coreboot code, but they
> > would make development easier, and that's a value in itself, especially
> > now that we're porting coreboot to laptops where a LPC bus may be the
> > only easily available bus at startup.
> >
> > Comments? Do we have mentors who can review VHDL/Verilog?
> >
> > Regards,
> > Carl-Daniel

GSoC project ideas

[Svetoslav Trochev]

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> I don't think age matters, as long as you are an student at a recognized
> school, google approves.

Sorry, you are right. The age doesn't matter in general. But in my
case it does. I graduated from Engineering School in mid-90's :)
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