[LinuxBIOS] Fwd: Re: smbus_write_byte

[Joseph Smith]

Quoting Marc Jones :
> Joseph Smith wrote:
> > Quoting Corey Osgood :
> > > yhlu wrote:
> > > > just provide one fake spd array...
> > > >
> > > > YH
> > >
> > > My thoughts exactly. You can't write to the smbus because there's no
> > > device on the smbus at that location to receive those writes.
> > >
> > > -Corey
> >
> > How would I provide a fake spd array? Here is the situation. My    
> > board  has the onboard memory without a SPD, I could just hardcode   
> >  this into  the northbridge raminit.c. But I don't want to do that   
> >  so people that  may want to use the northbridge src for other    
> > boards won't have to  deal with it. So right now I have auto.c call  
> >   a function that runs in  between sdram_set_spd_registers and    
> > sdram_enable, like this:
> >
> > sdram_set_spd_registers(memctrl);
> >    onboard_sdram_set_registers(memctrl);
> >    sdram_enable(0, memctrl);
> >
> > This function, onboard_sdram_set_registers manually sets up the regsters.
> >
> > Anyways I would also like to get the smbus_write_byte write going    
> > to  setup my tv-out registers on my tv-out chip?
> >
> > Thanks - Joe
>
> Joe,
> There is an example of an spd array in
> mainboard/artecgroup/dbe61/cache_as_ram_auto.c spd_read_byte(). You
> will have to generate the correct SPD values for your memory.
>
> Is the normal smbus_write_byte not working?
>
> Marc

Thanks everyone for your help. No, the smbus_write_byte is commented
out and has a big FIXME. I assume the code just never got finished??

static void smbus_write_byte(unsigned device, unsigned address,
unsigned char val)
{
    if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
    	return;
    }

print_debug("Unimplemented smbus_write_byte() called.\r\n");

#if 0
    /* setup transaction */
    /* disable interrupts */
    outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
    		SMBUS_IO_BASE + SMBGCTL);
    /* set the device I'm talking too */
    outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
    outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
    /* set up for a byte data write */ /* FIXME */
    outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
    /* clear any lingering errors, so the transaction will run */
    /* Do I need to write the bits to a 1 to clear an error? */
    outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);

/* clear the data word...*/
    outw(val, SMBUS_IO_BASE + SMBHSTDAT);

/* start the command */
    outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);

/* poll for transaction completion */
    smbus_wait_until_done(SMBUS_IO_BASE);
#endif
    return;
}

Thanks - Joe

[Corey Osgood]

Joseph Smith wrote:
> Quoting Marc Jones :
> > Joseph Smith wrote:
> > > Quoting Corey Osgood :
> > > > yhlu wrote:
> > > > > just provide one fake spd array...
> > > > >
> > > > > YH
> > > >
> > > > My thoughts exactly. You can't write to the smbus because there's no
> > > > device on the smbus at that location to receive those writes.
> > > >
> > > > -Corey
> > >
> > > How would I provide a fake spd array? Here is the situation. My  
> > > board  has the onboard memory without a SPD, I could just hardcode 
> > >  this into  the northbridge raminit.c. But I don't want to do that 
> > >  so people that  may want to use the northbridge src for other  
> > > boards won't have to  deal with it. So right now I have auto.c call
> > >   a function that runs in  between sdram_set_spd_registers and  
> > > sdram_enable, like this:
> > > sdram_set_spd_registers(memctrl);
> > > onboard_sdram_set_registers(memctrl);
> > > sdram_enable(0, memctrl);
> > >
> > > This function, onboard_sdram_set_registers manually sets up the
> > > regsters.
> > >
> > > Anyways I would also like to get the smbus_write_byte write going  
> > > to  setup my tv-out registers on my tv-out chip?
> > >
> > > Thanks - Joe
> >
> > Joe,
> > There is an example of an spd array in
> > mainboard/artecgroup/dbe61/cache_as_ram_auto.c spd_read_byte(). You
> > will have to generate the correct SPD values for your memory.
> >
> > Is the normal smbus_write_byte not working?
> >
> > Marc
>
> Thanks everyone for your help. No, the smbus_write_byte is commented
> out and has a big FIXME. I assume the code just never got finished??

Hmm, smbus_write_byte is commented in the original code
(intel/i82801db/i82801db_early_smbus.c), but smbus_write_block is not,
so it should work with the comments removed. Does that help at all?

-Corey
> static void smbus_write_byte(unsigned device, unsigned address,
> unsigned char val)
> {
>     if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
>         return;
>     }
> print_debug("Unimplemented smbus_write_byte() called.\r\n");
>
> #if 0
>     /* setup transaction */
>     /* disable interrupts */
>     outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
>             SMBUS_IO_BASE + SMBGCTL);
>     /* set the device I'm talking too */
>     outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
>     outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
>     /* set up for a byte data write */ /* FIXME */
>     outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE +
> SMBGCTL);
>     /* clear any lingering errors, so the transaction will run */
>     /* Do I need to write the bits to a 1 to clear an error? */
>     outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
> /* clear the data word...*/
> outw(val, SMBUS_IO_BASE + SMBHSTDAT);
>
> /* start the command */
> outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE +
>
> SMBGCTL);
> /* poll for transaction completion */
> smbus_wait_until_done(SMBUS_IO_BASE);
>
> #endif
>     return;
> }
>
> Thanks - Joe

[Joseph Smith]

> > Joe,
> > There is an example of an spd array in
> > mainboard/artecgroup/dbe61/cache_as_ram_auto.c spd_read_byte(). You
> > will have to generate the correct SPD values for your memory.
> >
> > Marc

Cool!! So let me get this straight. The function spd_read_byte() in  
cache_as_ram_auto.c is re-defining the spd_read_byte() function from  
src/southbridge/amd/cs5536/cs5536_early_smbus.c correct?
And it is saying that if the device is DIMM0 (0xA0) to read from the array?
So what if it is DIMM1 (0xA2)? Does it use the normal spd_read_byte()  
from cs5536_early_smbus.c?

Thanks - Joe

[Marc Jones]

Joseph Smith wrote:
> > > Joe,
> > > There is an example of an spd array in
> > > mainboard/artecgroup/dbe61/cache_as_ram_auto.c spd_read_byte(). You
> > > will have to generate the correct SPD values for your memory.
> > >
> > > Marc
>
> Cool!! So let me get this straight. The function spd_read_byte() in  
> cache_as_ram_auto.c is re-defining the spd_read_byte() function from  
> src/southbridge/amd/cs5536/cs5536_early_smbus.c correct?
> And it is saying that if the device is DIMM0 (0xA0) to read from the array?
> So what if it is DIMM1 (0xA2)? Does it use the normal spd_read_byte()  
> from cs5536_early_smbus.c?
>
> Thanks - Joe

No, If it is 0xA2 it returns 0xFF as if the spd is not there.
Marc

[Joseph Smith]

Quoting Marc Jones :
> Joseph Smith wrote:
> > > > Joe,
> > > > There is an example of an spd array in
> > > > mainboard/artecgroup/dbe61/cache_as_ram_auto.c spd_read_byte(). You
> > > > will have to generate the correct SPD values for your memory.
> > > >
> > > > Marc
> >
> > Cool!! So let me get this straight. The function spd_read_byte() in  
> >   cache_as_ram_auto.c is re-defining the spd_read_byte() function   
> > from  src/southbridge/amd/cs5536/cs5536_early_smbus.c correct?
> > And it is saying that if the device is DIMM0 (0xA0) to read from the array?
> > So what if it is DIMM1 (0xA2)? Does it use the normal   
> > spd_read_byte()  from cs5536_early_smbus.c?
> >
> > Thanks - Joe
>
> No, If it is 0xA2 it returns 0xFF as if the spd is not there.
> Marc

Oh, then I would have to switch it up a bit. This should work ok right?
---------------------
static int spd_read_byte(unsigned device, unsigned address)
{
    int i;

if (device == 0x50){
    	return do_smbus_read_byte(device, address);
    } else if (device == 0x51){
    	for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
    		if (spd_table[i].address == address){
    			return spd_table[i].data;
    		}
    	}
    } else {
    	return 0xFF; /* returns 0xFF on any failures */
    }
}
---------------------

Thanks - Joe

[Marc Jones]

Joseph Smith wrote:
> Quoting Marc Jones :
> > Joseph Smith wrote:
> > > > > Joe,
> > > > > There is an example of an spd array in
> > > > > mainboard/artecgroup/dbe61/cache_as_ram_auto.c spd_read_byte(). You
> > > > > will have to generate the correct SPD values for your memory.
> > > > >
> > > > > Marc
> > >
> > > Cool!! So let me get this straight. The function spd_read_byte() in   
> > > cache_as_ram_auto.c is re-defining the spd_read_byte() function  
> > > from  src/southbridge/amd/cs5536/cs5536_early_smbus.c correct?
> > > And it is saying that if the device is DIMM0 (0xA0) to read from the 
> > > array?
> > > So what if it is DIMM1 (0xA2)? Does it use the normal  
> > > spd_read_byte()  from cs5536_early_smbus.c?
> > >
> > > Thanks - Joe
> >
> > No, If it is 0xA2 it returns 0xFF as if the spd is not there.
> > Marc
> Oh, then I would have to switch it up a bit. This should work ok right?
>
> static int spd_read_byte(unsigned device, unsigned address)
> {
>     int i;
> if (device == 0x50){
>     return do_smbus_read_byte(device, address);
> } else if (device == 0x51){
>     for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
>         if (spd_table[i].address == address){
>             return spd_table[i].data;
>         }
>     }
> } else {
>     return 0xFF; /* returns 0xFF on any failures */
> }
> }
>
> Thanks - Joe

That looks like it should do what you want.
Marc