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hi, maybe this would be a good start for a decent source code documentation. at least it should help understanding the code. Holger
/** * * HOW INTEL FX/VX/HX/TX DRAM BOUNDARY WORKS * ----------------------------------------- * * Allowing the user to install different types and sizes of memory to a main- * board makes it hard for the chipset to correctly apply the right signals to * the memory modules. It is the task of the BIOS programmer to detect the * size and type of the modules and report the findings to the chipset by * setting registers. * Intel uses the so called DRAM boundary register (DRB) to keep track of the * module size and design installed in a system. Each DRB will hold the boundary * addresses in 4MB granularity plus the boundary addresses of all DRBs before. * The detection of memory must start with the first DRB and end with the last. * The last DRB will hold the total amount of memory installed in the sytem. * A memory row in a system is defined as one 64bit broad memory array. * As 72pin SIMM modules have a 32bit board data interface, two of them are * needed to form one row. The first module will be called SIMM1, the second * SIMM2 and so on. * The modules can be single sided or double sided. Modules with chips on both * sides are generally called double sided which may not be true. Double sided * refers to the number of memory control signals used by the module to address * its memory. Since the detection algorithm isn't able to actually see the * module it doesn't matter if it has chips on both sides or not. The algorithm * will just assume the module is double sided and maybe revise its descicion * after some tests. But more on that later. Take a look at figure 1. It shows * the memory array configuration of a typical Intel 430FX mainboard with * 4 SIMMs. * * * 32bit 32bit * <-----------> <-----------> * 64bit * <-------------------------> * * SIMM4 back SIMM3 back * ## ## ## ## ## ## ## ## <- DRB4 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB3 * SIMM4 front SIMM3 front * * SIMM2 back SIMM1 back * ## ## ## ## ## ## ## ## <- DRB2 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB1 * SIMM2 front SIMM1 front * * ## ## ## ## ## ## ## ## <- DRB0 * onboard memory * FIGURE 1: Memory array configuration of a typical Intel 430FX mainboard * * You might have noticed one thing by now: DRB0 is pointing to onboard memory. * Intel included the option to install a single sided row of memory directly on * the mainboard. This would allow the mainboard manufacturer to solder some * memory directly to the mainboard and give the option to install more modules * in SIMM sockets. These mainboards would end up in the OEM market used in * cheap work horses like office machines or terminals. While it doesn't affect * the algorithm at all, it still is good to know if some strange results may * show up. * * To make things easier we'll use a slightly different memory array * configuration seen in figure 2. * * * 32bit 32bit * <-----------> <-----------> * 64bit * <-------------------------> * * SIMM4 back SIMM3 back * ## ## ## ## ## ## ## ## <- DRB3 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB2 * SIMM4 front SIMM3 front * * SIMM2 back SIMM1 back * ## ## ## ## ## ## ## ## <- DRB1 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB0 * SIMM2 front SIMM1 front * FIGURE 2: Memory array configuration of an imaginary Intel 430FX mainboard * * Now that's what the majority of Intel 430FX boards look like! This should * look quite familiar: SIMM1/SIMM2 form one row of memory and SIMM3/SIMM4 the * other. * The maximum size of memory the Intel 430FX can handle is 128MB. So if we have * 4 memory modules which have to be installed in pairs each pair must have 64MB * and each module of the pair must have 32MB. * * Let's start with an easy example: installing two memory modules, 16MB each, * single sided. Figure 3 shows what the memory configuration would look like. * * 32bit 32bit * <-----------> <-----------> * 64bit * <-------------------------> * * SIMM2 back SIMM1 back * <- DRB1 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB0 * SIMM2 front SIMM1 front * FIGURE 3: Memory array configuration for two 16MB single sided SIMMs * * Since two modules always form one row we would have now 32MB installed in one * row. After proper detection the DRB registers would look like in table 1. * * DRB0: 08h (32MB installed) * DRB1: 08h (empty) * DRB2: 08h (empty) * DRB3: 08h (empty) * DRB4: 08h (empty) * TABLE 1: DRB register values for a memory configuration of two 16MB single * sided SIMMs * * As we can see even if there is no memory installed in a row the amount of the * DRB before has to be filled in, making the total amount of memory available * in DRB4. * Let's take another pair of those memory modules and install them in the two * remaining SIMM sockets. There are now 4 single sided modules installed, 16MB * each resulting in 64MB total. Figure 4 shows the acutal memory configuration. * * 32bit 32bit * <-----------> <-----------> * 64bit * <-------------------------> * * SIMM4 back SIMM3 back * <- DRB3 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB2 * SIMM4 front SIMM3 front * * SIMM2 back SIMM1 back * <- DRB1 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB0 * SIMM2 front SIMM1 front * FIGURE 4: Memory array configuration for four 16MB single sided SIMMs * * Since two modules always form one row we would have now 32MB installed in one * row and 64MB installed in the whole system. After proper detection the DRB * registers would look like in table 2. * * DRB0: 08h (32MB installed) * DRB1: 08h (empty) * DRB2: 10h (32MB installed) * DRB3: 10h (empty) * DRB4: 10h (empty) * TABLE 2: DRB register values for a memory configuration of four 16MB single * sided SIMMs * * The last example shows the memory configuration of two 32MB double sided * SIMMs installed in SIMM1/2. Figure 5 shows the actual memory configuration. * * 32bit 32bit * <-----------> <-----------> * 64bit * <-------------------------> * * SIMM2 back SIMM1 back * ## ## ## ## ## ## ## ## <- DRB1 * ------------- ------------- * ## ## ## ## ## ## ## ## <- DRB0 * SIMM2 front SIMM1 front * FIGURE 5: Memory array configuration for two 32MB double sided SIMMs * * As you can see row 1 is not empty anymore and thus resulting in the DRB * setup shown in table 3. * * DRB0: 08h (32MB installed, 1st half of the 64MB) * DRB1: 10h (32MB installed, 2nd half of the 64MB) * DRB2: 10h (empty) * DRB3: 10h (empty) * DRB4: 10h (empty) * TABLE 2: DRB register values for a memory configuration of two 32MB double * sided SIMMs *
Hi,
On Sun, Aug 12, 2007 at 04:05:32PM +0200, popkonserve wrote:
maybe this would be a good start for a decent source code documentation. at least it should help understanding the code.
Yep, great thanks! Assuming you wrote this from scratch (vs. copying from somewhere), please add this to your code so we can include it when committing...
- The modules can be single sided or double sided. Modules with chips on both
- sides are generally called double sided which may not be true. Double sided
- refers to the number of memory control signals used by the module to address
- its memory. Since the detection algorithm isn't able to actually see the
- module it doesn't matter if it has chips on both sides or not. The algorithm
- will just assume the module is double sided and maybe revise its descicion
^^^^^^^^^ decision
- Let's take another pair of those memory modules and install them in the two
- remaining SIMM sockets. There are now 4 single sided modules installed, 16MB
- each resulting in 64MB total. Figure 4 shows the acutal memory configuration.
^^^^^^ actual
Cheers, Uwe.
-
Janek Kozicki -
popkonserve -
Uwe Hermann