Does anyone have an idea what the status of Intel's poulsbou in current coreboot is? - cmc contained no mem config. So I dumped the registers from the running system (sch, port1, reg0..2) from the running system and filled out sysinfo->ranks, cl, trcd, trp, device_density, data_width based on those values. - I noticed that my FSB runs at 533MHz. So I set the lower bit in SCH_MSG_DUNIT_REG_DCO (the orignial code sets BIT 0 if FSB is 533 but then throwes it away and writes 0x006911c).
Now: - The SCH register 2, 8 is set to 0x40000000 (1GiB). The original BIOS sets this to 0x80000000 (2GiB) which would also match the magic with data_width, ranks & device_density which result is overwritten. Is this correct? What is the purpose of this value?
- In sch_shadow_CMC(). I have no idea why cpuid_eax(0x80000008) should be written in that register. I haven't found any documentation claiming that it should be done. The system hangs after executing a wbinvd like the manual says. That is probably why the cmc code is copied twice and the wbinvd is commented out. It hangs mostlikely due to the CAR setup. So maybe it could be moved to southbridge setup somewhere.
- in src/northbridge/intel/sch/northbridge.c, pci_domain_set_resources() is using PCI device (0,0) register 0x9c is used to figure out how much memory is available. I read 0x0 here in original bios and coreboot. I assigned 1 GiB here for the variable. Is this a BIOS set variable? This file / function looks like a copy of src/northbridge/intel/i945/northbridge.c. For TOM it could be SCH (2, 8) because this is written by sdram_initialize() (with the wrong value in my setup however). It is just a guess however. The next part reads GGC register and I belive from wrong device as it should be PCI_DEVFN(2, 0). Atlteast it is written in iWRainbowG6's romstage.c TSEG is read from pci dev (0,0) register 0x9e. I'm not sure this is correct, I don't see any place that this is written.
- I extraced the VGA ROM from the BIOS. After attaching it I see three unhandled INT15 calls with AX=0x5f35, AX=0x5f40, AX=0x5f35. After that coreboot continues, display remains blank. Is it possible to emulate these calls to get some output? Linux somehow des not do anything right now…
- After booting I get errors from the ehci controller after attaching a highspeed device. Attaching a keyboard seems to works. Is there something I have to tweak to get highspeed USB working?
I could send patches for some of things but I am not always sure what I do :)
Sebastian
Sebastian Andrzej Siewior wrote:
Does anyone have an idea what the status of Intel's poulsbou in current coreboot is?
I think the status is that it maybe runs on one specific hardware which noone really has access to.
- I extraced the VGA ROM from the BIOS. After attaching it I see three unhandled INT15 calls with AX=0x5f35, AX=0x5f40, AX=0x5f35. After that coreboot continues, display remains blank. Is it possible to emulate these calls to get some output?
Suggest don't run the VGA BIOS in coreboot. We really need to change the default. Please run the VGA BIOS only using SeaBIOS as payload.
I guess those services are to query system-specific data. Look at what has been implemented in coreboot and SeaBIOS already for this.
- After booting I get errors from the ehci controller after attaching a highspeed device. Attaching a keyboard seems to works. Is there something I have to tweak to get highspeed USB working?
Probably several things.
I could send patches for some of things but I am not always sure what I do :)
Please push commits to Gerrit. See http://www.coreboot.org/Git
//Peter
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Peter Stuge -
Sebastian Andrzej Siewior