New patch to review for coreboot: 3eb82eb Intel cpus: cache actual size of the Flash ROM device
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/641
-gerrit
commit 3eb82ebe06369ad6f278319989c3c574a3c9264a Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Thu Feb 16 20:11:31 2012 +0200
Intel cpus: cache actual size of the Flash ROM device
Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded using model_6ex CAR implementation. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory.
Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary.
Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/intel/model_6ex/cache_as_ram.inc | 9 ++++++--- src/mainboard/Kconfig | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 8f2b1bd..cbfa4f8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -24,6 +24,9 @@
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1)
+/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -190,13 +193,13 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr
- /* Enable caching and Speculative Reads for the last 4MB. */ + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index cc4e14f..a34bd85 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -285,6 +285,10 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
+config CACHE_ROM_SIZE + hex + default ROM_SIZE + config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL default y if POWER_BUTTON_DEFAULT_ENABLE
-
Kyösti Mälkki