[commit] r6212 - in trunk/src: drivers/dec/21143 mainboard/hp/dl145_g1 mainboard/hp/dl145_g3 mainboard/hp/dl165_g6_fam10 mainboard/nokia/ip530 southbridge/ti/pci1x2x
Author: uwe Date: Sun Dec 26 15:12:38 2010 New Revision: 6212 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6212
Log: Random fixes for TI pci1x2x / Nokia IP530 / others.
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c: - Fix SMSC FDC37B787 name (was a typo). - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either. - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/. - All of these are confirmed by Marc Bertens on IRC.
- Fix a few CHIP_NAME HP board names.
- Random whitespace and coding-style fixes.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/drivers/dec/21143/21143.c trunk/src/mainboard/hp/dl145_g1/mainboard.c trunk/src/mainboard/hp/dl145_g3/mainboard.c trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/southbridge/ti/pci1x2x/pci1x2x.c
Modified: trunk/src/drivers/dec/21143/21143.c ============================================================================== --- trunk/src/drivers/dec/21143/21143.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/drivers/dec/21143/21143.c Sun Dec 26 15:12:38 2010 (r6212) @@ -38,33 +38,40 @@ /* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
/** - * This driver take the values from Kconfig and load them in the registers + * This driver takes the values from Kconfig and loads them in the registers. */ -static void dec_21143_enable( device_t dev ) +static void dec_21143_enable(device_t dev) { - printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n"); - // Command and Status Configuration Register (Offset 0x04) - pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); - printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); - // Cache Line Size Register (Offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE ); - printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) ); - // Expansion ROM Base Address Register (Offset 0x30) - pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS ); - printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) ); - return; + printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); + + /* Command and status configuration (offset 0x04) */ + pci_write_config32(dev, 0x04, + CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION); + printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", + pci_read_config32(dev, 0x04)); + + /* Cache line size (offset 0x0C) */ + pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE); + printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", + pci_read_config32(dev, 0x0C)); + + /* Expansion ROM base address (offset 0x30) */ + pci_write_config32(dev, 0x30, + CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS); + printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", + pci_read_config32(dev, 0x30)); }
-static struct device_operations dec_21143_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = dec_21143_enable, - .scan_bus = 0, +static struct device_operations dec_21143_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = dec_21143_enable, + .scan_bus = 0, };
static const struct pci_driver dec_21143_driver __pci_driver = { - .ops = &dec_21143_ops, - .vendor = PCI_VENDOR_ID_DEC, - .device = PCI_DEVICE_ID_DEC_21142, + .ops = &dec_21143_ops, + .vendor = PCI_VENDOR_ID_DEC, + .device = PCI_DEVICE_ID_DEC_21142, };
Modified: trunk/src/mainboard/hp/dl145_g1/mainboard.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/mainboard.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/hp/dl145_g1/mainboard.c Sun Dec 26 15:12:38 2010 (r6212) @@ -25,5 +25,5 @@ #include "chip.h"
struct chip_operations mainboard_ops = { - CHIP_NAME("HP DL145G1 Mainboard") + CHIP_NAME("HP ProLiant DL145 G1 Mainboard") };
Modified: trunk/src/mainboard/hp/dl145_g3/mainboard.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/mainboard.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/hp/dl145_g3/mainboard.c Sun Dec 26 15:12:38 2010 (r6212) @@ -30,5 +30,5 @@ #include "chip.h"
struct chip_operations mainboard_ops = { - CHIP_NAME("HP DL145 G3 Mainboard") + CHIP_NAME("HP ProLiant DL145 G3 Mainboard") };
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c Sun Dec 26 15:12:38 2010 (r6212) @@ -30,5 +30,5 @@ #include "chip.h"
struct chip_operations mainboard_ops = { - CHIP_NAME("HP DL165 G6 Mainboard (Family 10)") + CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)") };
Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Sun Dec 26 15:12:38 2010 (r6212) @@ -19,9 +19,9 @@ ##
chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/intel/socket_PGA370 # CPU socket + device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain @@ -29,7 +29,7 @@ device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878) + chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) device pnp 3f0.3 off end # Parallel port (No connector) device pnp 3f0.4 on # COM1 @@ -40,10 +40,10 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.7 on end # PS/2 keyboard / mouse device pnp 3f0.6 on end # RTC + device pnp 3f0.7 off end # PS/2 keyboard / mouse (No connector) device pnp 3f0.8 on end # AUX I/O - device pnp 3f0.A off end # ACPI (No support yet) + device pnp 3f0.a off end # ACPI (No support yet) end end device pci 7.1 on end # IDE
Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Sun Dec 26 15:12:38 2010 (r6212) @@ -24,41 +24,43 @@ #include <device/pci_ops.h> #include <console/console.h>
-#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) ) +#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR)) #error "you must supply these values in your mainboard-specific Kconfig file" #endif
static void ti_pci1x2y_init(struct device *dev) { printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); - // Command register (offset 04) - pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR ); - // Cache Line Size Register (offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR ); - // CardBus latency timer register (offset 1B) - pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR ); - // Bridge control register (offset 3E) - pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR ); - /** Enable change sub-vendor id - * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */ - pci_write_config32( dev, 0x80, 0x10 ); - pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA ); - // Now write the correct value for SCR - // System Control Register (offset 0x80) - pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR ); - // Multifunction routing register - pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR ); - // Set Device Control Register (0x92) accordingly - pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 ); - return; + + /* Command (offset 04) */ + pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR); + /* Cache Line Size (offset 0x0C) */ + pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR); + /* CardBus latency timer (offset 0x1B) */ + pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR); + /* Bridge control (offset 0x3E) */ + pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR); + /* + * Enable change sub-vendor ID. Clear the bit 5 to enable to write + * to the sub-vendor/device ids at 40 and 42. + */ + pci_write_config32(dev, 0x80, 0x10); + pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); + /* Now write the correct value for SCR. */ + /* System control (offset 0x80) */ + pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR); + /* Multifunction routing */ + pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR); + /* Set the device control register (0x92) accordingly. */ + pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); }
-static struct device_operations ti_pci1x2y_ops = { +static struct device_operations ti_pci1x2y_ops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -67,19 +69,19 @@ };
static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1225, + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1225, };
static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1420, + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1420, };
static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1420, + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1520, };
On 12/26/10 3:12 PM, repository service wrote:
Modified: trunk/src/drivers/dec/21143/21143.c
--- trunk/src/drivers/dec/21143/21143.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/drivers/dec/21143/21143.c Sun Dec 26 15:12:38 2010 (r6212) @@ -38,33 +38,40 @@
- /* Command and status configuration (offset 0x04) */
- pci_write_config32(dev, 0x04,
CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION);- printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n",
pci_read_config32(dev, 0x04));- /* Cache line size (offset 0x0C) */
- pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE);
- printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n",
pci_read_config32(dev, 0x0C));- /* Expansion ROM base address (offset 0x30) */
- pci_write_config32(dev, 0x30,
CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS);
This does not seem to make much sense for the 21143 ... Why is it needed? Generally such stuff does not belong in Kconfig, but in this particular case the resource allocator should do the right thing already.
- printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n",
pci_read_config32(dev, 0x30));}
Merry christmas, Stefan
-
repository service -
Stefan Reinauer